Skyworks Solutions Inc. SI5338N-A-GM
- Part No.:
- SI5338N-A-GM
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Application Specific Clock/Timing
- Package:
- 24-VFQFN Exposed Pad
- Datasheet:
-
SI5338N-A-GM.pdf
- Description:
- IC CLK GEN I2C BUS PROG 24QFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SI5338N-A-GM from Skyworks Solutions is an I²C-programmable quad clock generator IC with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation from 1.8/2.5/3.3 V core supply in a 4 × 4 mm 24-QFN package. It replaces up to four crystal oscillators in high-speed serial interface timing applications.
For engineers reviewing the SI5338N-A-GM datasheet, SI5338N-A-GM pinout, SI5338N-A-GM application, or SI5338N-A-GM equivalent, key selection criteria include its MultiSynth™-based any-frequency synthesis (0.16–710 MHz per output), independent output voltage control (1.5–3.3 V), programmable phase/frequency adjustment (±45 ns / 1 ppm steps), spread-spectrum capability (0.5–5.0% down-spread), and loss-of-lock/loss-of-signal alarm support.
Technical Context
The SI5338N-A-GM implements a two-stage PLL architecture: a high-stability reference stage (with crystal or external clock input) followed by four independent MultiSynth™ fractional-N synthesis paths, each feeding a configurable output driver stage. This enables true zero-ppm frequency accuracy across all outputs without requiring external loop filters.
Each output supports LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats with independent VDDO supply (1.4–3.63 V), selectable slew rate, and programmable termination. Input flexibility includes differential (5–710 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), or 8–30 MHz crystal reference - all routed through a shared input multiplexer with automatic detection.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Phase Jitter (RMS) | 0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 3 SRNS & Gen 4 common clock jitter requirements |
| Output Frequency Range | 0.16–710 MHz per channel; supports integer/fractional synthesis with 1 ppb resolution |
| Input Reference Options | Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz) |
| Output Formats | LVPECL, LVDS, HCSL, CML, CMOS, SSTL, HSTL - each output independently configurable |
| Supply Voltages | Core: 1.8/2.5/3.3 V ±10%; Output buffers: 1.4–3.63 V per VDDO rail |
| Operating Temperature | –40 °C to +85 °C; qualified for industrial and telecom line card environments |
| Package | 24-pin QFN, 4 × 4 mm, 0.5 mm pitch; RoHS-compliant, moisture sensitivity level 3 |
Pinout & Package
The SI5338N-A-GM is housed in a 24-lead, 4 × 4 mm QFN package with exposed thermal pad. Pin assignments are fixed per Skyworks' Si5338 family layout and include four differential clock outputs (CLK0A/B through CLK3A/B), six input pins (IN1–IN6), I²C interface (SCL/SDA), interrupt (INTR), power (VDD, VDDO0–VDDO3), ground (GND), and reserved ground (RSVD_GND).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CLK0A / CLK0B | Differential Output Pair 0 | LVPECL/LVDS/HCSL/CML-capable; independently voltage- and format-configurable |
| CLK1A / CLK1B | Differential Output Pair 1 | Supports same signal formats and frequency range as CLK0; isolated synthesis path |
| CLK2A / CLK2B | Differential Output Pair 2 | Configurable independently; enables multi-domain clocking (e.g., PCIe + Ethernet + FPGA) |
| CLK3A / CLK3B | Differential Output Pair 3 | Final output pair; supports HCSL up to 250 MHz or LVDS up to 710 MHz |
| IN1 / IN2, IN5 / IN6 | Differential Input Pairs | Accept 5–710 MHz AC-coupled signals; internal 100 Ω termination option |
| IN3 / IN4 | Single-Ended Inputs | Support CMOS/SSTL/HSTL; 5–350 MHz range; internal biasing and threshold control |
| SCL / SDA | I²C Serial Interface | Standard-mode (100 kHz) and fast-mode (400 kHz) compatible; SMBus-level pull-up support |
| INTR | Interrupt Output | Open-drain status flag for loss-of-lock, loss-of-signal, or configuration error events |
| VDD | Core Supply | 1.8/2.5/3.3 V ±10%; supplies PLL, logic, and memory; PSRR > 60 dB @ 100 kHz |
| VDDO0–VDDO3 | Output Buffer Supplies | Independent 1.4–3.63 V rails per output pair; enable mixed-voltage system interfacing |
| GND / RSVD_GND | Ground Terminals | Four dedicated GND pins plus one reserved ground; low-inductance return path for noise-sensitive analog blocks |
Key Features
| Feature | Design Value |
|---|---|
| MultiSynth™ Any-Frequency Synthesis | Four independent fractional-N synthesizers deliver exact frequencies (0.16–710 MHz) with 0 ppm error - eliminates need for multiple crystals or custom oscillators |
| PCIe Gen 1–4 Timing Compliance | Meets Common Clock (Gen 1/2/3/4) and Gen 3 Separate Reference No Spread (SRNS) jitter specs - validated using Intel Clock Jitter Tool |
| Independent Output Voltage Control | Each of four VDDO rails (VDDO0–VDDO3) sets output driver voltage (1.5/1.8/2.5/3.3 V), enabling direct interface to mixed-voltage FPGAs, ASICs, and SerDes |
| Programmable Phase/Frequency Adjustment | Glitchless ±45 ns phase shift and 1 ppm frequency increment/decrement via pin or I²C - supports dynamic clock tuning in live systems |
| Spread Spectrum Clocking (SSC) | Configurable down-spread (0.5–5.0%) and modulation rate (33–63 kHz) on any output - reduces EMI without affecting timing margin |
| Loss-of-Lock & Loss-of-Signal Detection | Dedicated INTR pin asserts within 10 ms of PLL unlock or input failure - enables system-level fault recovery and redundancy switching |
Applications
| PCIe Gen 3/4 Root Complex | Ethernet Switch Timing |
|---|---|
Use Scenario: Providing synchronized 100 MHz reference clocks to CPU, GPU, and NVMe controllers in server motherboards with PCIe Gen 3/4 lanes. IC Role / Device Role / Timing Role: Quad-output clock generator delivering Common Clock topology with <0.32 ps RMS jitter (SRNS mode) and independent SSC per lane group. Use Value: Enables full Gen 4 x16 link training without retiming; eliminates inter-lane skew and meets PCIe Base Spec 4.0 jitter limits. | Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10/25 GbE PHYs and switch fabric in enterprise routers. IC Role / Device Role / Timing Role: Multi-format clock source supporting LVDS (PHY), HCSL (SerDes), and CMOS (control logic) simultaneously from one device. Use Value: Reduces BOM count by replacing three discrete oscillators; maintains sub-1 ps RMS jitter across all rates under temperature variation. |
| Broadcast Video Synchronization | FPGA-Based Test Equipment |
Use Scenario: Delivering genlock-accurate 27 MHz, 74.25 MHz, and 148.5 MHz clocks to SDI transceivers and video processors in broadcast cameras and switchers. IC Role / Device Role / Timing Role: Precision clock synthesizer with programmable initial phase offset (±45 ns) and <20 ps step resolution for frame-aligned timing alignment. Use Value: Achieves sub-line jitter stability required for SMPTE ST 2081-10 12G-SDI; eliminates manual trim capacitor adjustments. | Use Scenario: Supplying variable-rate sampling clocks (10–500 MHz) and trigger synchronization signals to high-speed ADC/DAC modules in automated test systems. IC Role / Device Role / Timing Role: Reconfigurable clock engine with I²C-controlled frequency sweep and phase-coherent multi-output burst generation. Use Value: Enables real-time clock rate changes during test sequences without glitching; supports deterministic latency-critical stimulus/response timing. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad-output programmable clock generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5338B-A-GM | Same silicon; differs only in factory-programmed NVM contents - default configuration optimized for buffer mode, not full synthesis | Limited to pre-defined frequency sets; lacks full I²C reprogrammability in field | Select SI5338N-A-GM when full runtime frequency agility and custom MultiSynth™ configuration are required |
| LMK04832RHAR | Two-stage jitter cleaner + dual-loop PLL; higher integration but no crystal oscillator input; larger 48-QFN package | Requires external clean reference; better for ultra-low-jitter cleaning than flexible synthesis | Choose LMK04832RHAR when input clock is noisy and jitter cleaning dominates over frequency flexibility |
Compared with Si5338B-A-GM and LMK04832RHAR, the SI5338N-A-GM uniquely combines crystal-based self-contained synthesis, full I²C configurability, and compact 24-QFN packaging - making it optimal for space-constrained, multi-protocol systems needing field-updatable clock trees.
Availability
SI5338N-A-GM is available at Aetrix Electronics and suitable for PCIe Gen 4 server platforms, 10/25/100 GbE switch designs, and broadcast video equipment requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.
Supply support for SI5338N-A-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and mobile markets.
The SI5338N-A-GM belongs to Skyworks' Si5338 family of programmable clock generators, designed specifically for high-density, multi-protocol digital systems requiring precise, flexible, and low-jitter clock distribution without external components.
FAQ
What is the primary function of the SI5338N-A-GM in a system design?
The SI5338N-A-GM serves as a fully programmable quad-output clock generator that synthesizes up to four independent, precise clock frequencies from a single reference (crystal or external clock). Its MultiSynth™ architecture enables zero-ppm accuracy and supports protocols including PCIe Gen 1–4, Ethernet, and broadcast video - eliminating multiple discrete oscillators. The SI5338N-A-GM integrates PLL, synthesis, and configurable output drivers in one 4 × 4 mm QFN package.
Does the SI5338N-A-GM support crystal oscillator input, and what frequency range is valid?
Yes, the SI5338N-A-GM supports fundamental-mode parallel-resonant crystals from 8 MHz to 30 MHz. It includes on-chip load capacitance options (11–13 pF supported, 17–19 pF recommended) and automatic crystal drive level control (max 100 µW). The SI5338N-A-GM also accepts external CMOS, SSTL, HSTL, or differential clock inputs - providing full input flexibility beyond crystal-only operation.
How does the SI5338N-A-GM achieve PCIe Gen 4 compliance given its jitter specifications?
The SI5338N-A-GM achieves PCIe Gen 4 Common Clock compliance with ≤0.45 ps RMS jitter (1.5 MHz–50 MHz band) when configured per Skyworks' validated settings: PLL bandwidth 2–4 MHz, CDR = 10 MHz, and HCSL 100 MHz outputs. This performance is measured using the Skyworks PCIe Clock Jitter Tool and aligns with PCI-SIG Base Specification 4.0 rev. 0.5. The SI5338N-A-GM's low-noise VCO and optimized loop filter design ensure consistent results across temperature and voltage.
Can the SI5338N-A-GM generate different output formats simultaneously, such as LVDS and HCSL?
Yes, the SI5338N-A-GM supports mixed output formats across its four differential pairs: CLK0A/B may be configured as LVDS, CLK1A/B as HCSL, CLK2A/B as LVPECL, and CLK3A/B as CML - all simultaneously and independently. Each output has its own VDDO supply rail (1.4–3.63 V), allowing direct interface to devices with differing I/O standards without level-shifting circuitry. The SI5338N-A-GM's register map permits per-output format, voltage, and termination control via I²C.
Is ClockBuilder Pro software required to configure the SI5338N-A-GM, or can it be programmed in-system?
ClockBuilder Pro is optional for initial configuration and validation but not required for in-system programming. The SI5338N-A-GM features a standard I²C/SMBus interface (up to 400 kHz) that allows full register access, frequency updates, and feature control directly from host firmware. Factory-programmed configurations are stored in one-time-programmable (OTP) memory, while runtime changes persist until power cycle unless written to OTP. The SI5338N-A-GM supports both methods without hardware dependency on ClockBuilder Pro.
SI5338N-A-GM Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- MultiSynth™
- Package/Case:
- 24-VFQFN Exposed Pad
- Packaging:
- Tray
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- PLL:
- Yes
- Main Purpose:
- Ethernet, Fibre Channel, PCI Express (PCIe), Telecom
- Input:
- CML, CMOS, HCSL, HSCL, HSTL, LVDS, LVPECL, SSTL, Crystal
- Output:
- HCSL, HSTL, LVCMOS, LVDS, LVPECL, SSTL
- Number of Circuits:
- 1
- Ratio - Input:Output:
- 4:4
- Differential - Input:Output:
- Yes/Yes
- Frequency - Max:
- 710MHz
- Voltage - Supply:
- 1.71V ~ 3.63V
- Operating Temperature:
- -40°C ~ 85°C
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 24-QFN (4x4)
SI5338N-A-GM FAQ
1.How can I place an order for SI5338N-A-GM through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5338N-A-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5338N-A-GM reliable?
The price and inventory of SI5338N-A-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338N-A-GM is usually 5 days.
3.What payment methods are accepted for SI5338N-A-GM?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338N-A-GM transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5338N-A-GM?
SI5338N-A-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5338N-A-GM order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5338N-A-GM?
For technical support, including SI5338N-A-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338N-A-GM requirements.
6.How does Aetrix verify that SI5338N-A-GM is sourced from the original manufacturer or authorized distributors?
All SI5338N-A-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338N-A-GM meets industry standards.
7.What is the process for return or replacement of SI5338N-A-GM?
All SI5338N-A-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338N-A-GM, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5338N-A-GM part is unused and in its original packaging.
Return procedure for SI5338N-A-GM:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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