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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338N-B04259-GMR

Name: SI5338N-B04259-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338N-B04259-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338N-B04259-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338N-B04259-GMR.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5338N-B04259-GMR from Skyworks Solutions is a quad-output, I²C-programmable clock generator with MultiSynth™ frequency synthesis. It delivers four independent, any-frequency outputs (0.16–710 MHz) with 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and support for LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats. It replaces up to four crystal oscillators in high-speed serial interface timing applications.

For engineers reviewing the SI5338N-B04259-GMR datasheet, SI5338N-B04259-GMR pinout, SI5338N-B04259-GMR application, or SI5338N-B04259-GMR equivalent, key selection criteria include differential output jitter performance at 125 MHz (0.7 ps RMS), PCIe Gen 4 common clock compliance, independent per-output voltage control (1.5/1.8/2.5/3.3 V), and 24-QFN package compatibility with space-constrained FPGA/ASIC clock trees.

Technical Context

The SI5338N-B04259-GMR implements a two-stage PLL architecture: a high-stability reference PLL (Stage 1) locks to an external crystal (8–30 MHz) or clock input (5–710 MHz), followed by four independent MultiSynth™ fractional-N synthesizers (Stage 2) generating each output. Each synthesizer supports integer or fractional mode operation with <20 ps programmable phase step resolution and 1 ppm frequency increment/decrement capability.

Its output stage provides full format flexibility: four differential drivers (CLK0A/B through CLK3A/B) support LVPECL, LVDS, HCSL, CML, SSTL, or HSTL signaling, while CMOS outputs are available via single-ended configuration. All outputs feature independent supply rails (VDDO0–VDDO3), enabling mixed-voltage system clocking without level shifters.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps - Meets PCIe Gen 4 common clock TJ spec with margin; enables direct use in 10 GbE and Fibre Channel receivers without external jitter cleaners.
Output Frequency Range	0.16–710 MHz - Covers all standard serial interface rates (PCIe 1–4, 1G/10G Ethernet, SATA, SAS, USB 3.x) from a single device.
Input Reference Support	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), Differential (5–710 MHz) - Eliminates need for external buffer or level translation on reference inputs.
Output Format Flexibility	LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL - Per-output format selection allows native interface matching to FPGAs, processors, switches, and PHYs.
Supply Voltage Range	VDD = 1.8/2.5/3.3 V ±10%; VDDOx = 1.4–3.63 V - Supports modern low-voltage SoCs and legacy 3.3 V logic simultaneously.
Package	24-pin QFN, 4 × 4 mm - Enables high-density PCB layout in telecom line cards and server motherboard clock distribution networks.
Operating Temperature	–40 °C to +85 °C - Qualified for industrial and networking equipment deployment without derating.

Pinout & Package

SI5338N-B04259-GMR uses a 24-lead, 4 × 4 mm QFN package with exposed thermal pad. Pin assignments are fixed across the Si5338 family and validated per Skyworks Rev. 1.6 datasheet Figure 1 (Top View).

Pin/Terminal	Circuit Role	Design Meaning
IN1/IN2, IN5/IN6	Differential reference inputs	Accept 5–710 MHz AC-coupled LVDS/LVPECL/CML; internal 100 Ω termination enables direct connection to oscillator outputs.
IN3/IN4	Single-ended reference inputs	Support 5–200 MHz CMOS or 5–350 MHz SSTL/HSTL; 20 kΩ internal pull-up/pull-down simplifies board-level biasing.
CLK0A/CLK0B – CLK3A/CLK3B	Differential clock outputs	Four independent pairs; each configurable as LVPECL, LVDS, HCSL, CML, SSTL, or HSTL with dedicated VDDOx supply pins.
VDDO0–VDDO3	Output buffer supplies	Enable per-output voltage setting (1.5/1.8/2.5/3.3 V); decoupling required per output domain to suppress crosstalk.
SCL/SDA	I²C programming interface	Standard SMBus-compatible 100 kHz / 400 kHz operation; supports in-system reconfiguration without power cycle.
INTR	Interrupt output	Open-drain status flag indicating loss-of-lock or loss-of-signal; drives external microcontroller GPIO for real-time fault monitoring.

Key Features

Feature	Design Value
MultiSynth™ synthesis	Enables true zero-ppm frequency accuracy on all four outputs-critical for synchronous Ethernet and CPRI fronthaul timing.
Independent phase adjustment	±45 ns range in <20 ps steps-allows precise skew compensation between SerDes lanes or memory channels.
Spread spectrum control	Configurable 0.5–5.0% down-spread at 33–63 kHz on any output-reduces EMI in dense compute modules without affecting timing margins.
External feedback mode	Supports zero-delay clock distribution-enables deterministic latency alignment in packet-switched timing architectures.
Glitchless frequency tuning	1 ppm step size with pin-controlled increment/decrement-permits dynamic rate adaptation in adaptive bitrate video encoders.

Applications

PCIe Gen 4 Switch Timing	Ethernet Switch Synchronization
Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe Gen 4 switch ICs in a 1U server motherboard. IC Role / Device Role / Timing Role: Quad-output clock generator delivering four identical, low-jitter 100 MHz HCSL clocks compliant with PCIe Gen 4 Common Clock specification. Use Value: Eliminates four discrete oscillators and associated layout complexity while maintaining <0.45 ps RMS jitter required for Gen 4 link training stability.	Use Scenario: Generating 125 MHz and 156.25 MHz clocks for 10GbE PHYs and packet processor interfaces in a Layer 3 enterprise switch. IC Role / Device Role / Timing Role: Any-frequency synthesizer producing two independent frequencies from a single 25 MHz crystal reference. Use Value: Reduces BOM count and improves inter-chip skew control versus dual-oscillator solutions, enabling tighter hold-time margins on high-speed SerDes lanes.
Broadcast Video Master Clock	FPGA-Based Video Processing
Use Scenario: Delivering SMPTE ST 2082 (28.63636 GHz) pixel clock and auxiliary 74.25 MHz audio clock in a 4K/8K broadcast encoder. IC Role / Device Role / Timing Role: High-precision frequency translator converting a 27 MHz crystal into exact broadcast-standard frequencies with zero ppm error. Use Value: Avoids costly custom crystal oscillators and ensures frame-accurate genlock across multi-channel video processing pipelines.	Use Scenario: Supplying 300 MHz transceiver reference, 100 MHz system clock, and 50 MHz debug clock to a Xilinx Versal ACAP in a real-time vision system. IC Role / Device Role / Timing Role: Configurable quad clock source supporting mixed-signal FPGA domains with independent voltage and format per output. Use Value: Simplifies power domain isolation and eliminates external level translators, reducing PCB layer count and signal integrity risk.

PCIe Gen 4 Switch Timing

Ethernet Switch Synchronization

Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe Gen 4 switch ICs in a 1U server motherboard.

IC Role / Device Role / Timing Role: Quad-output clock generator delivering four identical, low-jitter 100 MHz HCSL clocks compliant with PCIe Gen 4 Common Clock specification.

Use Value: Eliminates four discrete oscillators and associated layout complexity while maintaining <0.45 ps RMS jitter required for Gen 4 link training stability.

Use Scenario: Generating 125 MHz and 156.25 MHz clocks for 10GbE PHYs and packet processor interfaces in a Layer 3 enterprise switch.

IC Role / Device Role / Timing Role: Any-frequency synthesizer producing two independent frequencies from a single 25 MHz crystal reference.

Use Value: Reduces BOM count and improves inter-chip skew control versus dual-oscillator solutions, enabling tighter hold-time margins on high-speed SerDes lanes.

Broadcast Video Master Clock

FPGA-Based Video Processing

Use Scenario: Delivering SMPTE ST 2082 (28.63636 GHz) pixel clock and auxiliary 74.25 MHz audio clock in a 4K/8K broadcast encoder.

IC Role / Device Role / Timing Role: High-precision frequency translator converting a 27 MHz crystal into exact broadcast-standard frequencies with zero ppm error.

Use Value: Avoids costly custom crystal oscillators and ensures frame-accurate genlock across multi-channel video processing pipelines.

Use Scenario: Supplying 300 MHz transceiver reference, 100 MHz system clock, and 50 MHz debug clock to a Xilinx Versal ACAP in a real-time vision system.

IC Role / Device Role / Timing Role: Configurable quad clock source supporting mixed-signal FPGA domains with independent voltage and format per output.

Use Value: Simplifies power domain isolation and eliminates external level translators, reducing PCB layer count and signal integrity risk.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output programmable clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5338A-B04259-GM	Same silicon die and pinout; factory-programmed OTP version with preloaded configuration stored in NVM.	No I²C programming required at power-up; faster boot time but inflexible post-deployment.	Select when production volume justifies OTP customization and field reconfiguration is unnecessary.
ICS853S01AGI-01LFT	Fixed-frequency, non-programmable quad LVDS clock generator; no MultiSynth™, no I²C, no spread spectrum.	Limited to one preset frequency set; lacks PCIe Gen 4 jitter performance and format flexibility.	Select only for cost-sensitive, static-clock applications where frequency agility is not required.

Compared with SI5338N-B04259-GMR, the Si5338A-B04259-GM offers identical performance with reduced firmware overhead but no runtime reprogramming, while the ICS853S01AGI-01LFT trades programmability and jitter performance for lower unit cost in fixed-frequency deployments.

Availability

SI5338N-B04259-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, 10GbE synchronization, and broadcast video master clocking requiring stable component supply and long-term lifecycle support.

Supply support for SI5338N-B04259-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure and mobile markets.

The Si5338 product line was designed for high-performance, multi-protocol clock generation in data center, telecom, and broadcast systems-emphasizing ultra-low jitter, flexible output formatting, and software-defined frequency agility.

FAQ

What is the maximum output frequency supported by SI5338N-B04259-GMR in LVPECL format?

The SI5338N-B04259-GMR supports LVPECL output frequencies up to 710 MHz, as specified in Table 6 of the Skyworks datasheet. This capability enables direct clocking of high-speed SerDes blocks in PCIe Gen 4 and 10G Ethernet PHYs without frequency multiplication. Operation above 350 MHz requires use of Fvco/4 or Fvco/6 synthesis paths, limiting simultaneous high-frequency outputs to two unique frequencies.

Does SI5338N-B04259-GMR support PCIe Gen 4 Separate Reference No Spread (SRNS) mode?

Yes, SI5338N-B04259-GMR meets PCIe Gen 4 SRNS requirements with 0.11–0.32 ps RMS jitter (typ/max) when configured with a PLL bandwidth of 2–5 MHz and CDR frequency of 10 MHz. This is verified per PCI Express Base Specification 4.0 rev. 0.5 and measured using the Skyworks PCIe Clock Jitter Tool, confirming suitability for root complex and endpoint timing in Gen 4 systems.

Can SI5338N-B04259-GMR generate different output voltages on each channel?

Yes, SI5338N-B04259-GMR provides independent VDDO0–VDDO3 supply pins, allowing each of its four output drivers to operate at 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This enables direct interfacing with mixed-voltage devices-for example, driving a 1.8 V FPGA transceiver bank and a 3.3 V legacy controller from the same SI5338N-B04259-GMR without external level shifters.

How is the SI5338N-B04259-GMR programmed during system operation?

The SI5338N-B04259-GMR is programmed via its I²C/SMBus-compatible interface (SCL/SDA pins), supporting standard 100 kHz and fast-mode 400 kHz operation. Configuration is performed using Skyworks' ClockBuilder Pro software, which generates register maps and validates settings against jitter and timing constraints before download to the device's on-chip NVM or RAM.

What is the minimum input reference frequency supported by SI5338N-B04259-GMR in PLL bypass mode?

In PLL bypass (clock buffer) mode, SI5338N-B04259-GMR supports input reference frequencies as low as 1 MHz on single-ended inputs (IN3/IN4) and 5 MHz on differential inputs (IN1/IN2, IN5/IN6). However, loss-of-signal detection is disabled below 5 MHz, so system-level monitoring must be implemented externally if reliability at sub-5 MHz operation is required.

SI5338N-B04259-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338N-B04259-GMR FAQ

1.How can I place an order for SI5338N-B04259-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338N-B04259-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338N-B04259-GMR reliable?

The price and inventory of SI5338N-B04259-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338N-B04259-GMR is usually 5 days.

3.What payment methods are accepted for SI5338N-B04259-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338N-B04259-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338N-B04259-GMR?

SI5338N-B04259-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338N-B04259-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338N-B04259-GMR?

For technical support, including SI5338N-B04259-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338N-B04259-GMR requirements.

6.How does Aetrix verify that SI5338N-B04259-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338N-B04259-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338N-B04259-GMR meets industry standards.

7.What is the process for return or replacement of SI5338N-B04259-GMR?

All SI5338N-B04259-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338N-B04259-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338N-B04259-GMR part is unused and in its original packaging.

Return procedure for SI5338N-B04259-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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