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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338N-B04337-GMR

Name: SI5338N-B04337-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338N-B04337-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338N-B04337-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338N-B04337-GMR.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5338N-B04337-GMR from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation from 1.8/2.5/3.3 V core supply in a 4 × 4 mm 24-QFN package. It replaces up to four crystal oscillators in FPGA, processor, and Ethernet switch timing systems.

For engineers reviewing the SI5338N-B043337-GMR datasheet, SI5338N-B04337-GMR pinout, SI5338N-B04337-GMR application, or SI5338N-B04337-GMR equivalent, key selection criteria include output format flexibility (LVPECL/LVDS/HCSL/CMOS/SSTL), independent per-output voltage (1.5–3.3 V), any-frequency synthesis down to 0.16 MHz, spread-spectrum control, and PCIe jitter compliance at Gen 4.

Technical Context

The SI5338N-B04337-GMR implements a two-stage PLL architecture: a high-stability reference PLL (Stage 1) locks to one of six input sources (crystal, CMOS, SSTL/HSTL, or differential), followed by four independent MultiSynth™ fractional-N synthesizers (Stage 2) generating outputs with true zero-ppm accuracy. Each output supports programmable phase offset (<20 ps steps), frequency increment/decrement (1 ppm steps), and spread-spectrum modulation (0.5–5.0% spread, 33–63 kHz rate).

It features loss-of-lock and loss-of-signal alarms, external feedback for zero-delay mode, and I²C/SMBus interface with ClockBuilder Pro configuration support. The device operates across –40 to +85 °C and delivers <100 ps output-to-output skew under matched conditions.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 4 common clock jitter spec (≤0.45 ps RMS)
Output Count & Type	4 differential clock outputs (CLK0A/B–CLK3A/B); supports LVPECL/LVDS/HCSL/CML/SSTL/HSTL/CMOS
Frequency Range	0.16–710 MHz per output; integer/fractional synthesis with 1 ppb resolution
Input Flexibility	6 inputs: crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz)
Supply Voltages	Core: 1.8/2.5/3.3 V ±10%; output buffers: independently configurable 1.5/1.8/2.5/3.3 V
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch, exposed thermal pad
Operating Temp	–40 °C to +85 °C ambient; 150 °C max junction temperature

Pinout & Package

SI5338N-B04337-GMR is housed in a 24-lead, 4 × 4 mm QFN package with wettable flanks and an exposed thermal pad. Pin 1 is top-left corner (IN1), pin numbering proceeds counterclockwise. GND pins are at positions 19, 20, 21, and 23; VDD core supply is on pins 9 and 10; VDDOx supplies are dedicated per output group (VDDO0–VDDO3).

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2	Differential input pair #1	Accepts 5–710 MHz AC-coupled differential clock; requires external 100 Ω termination
IN3, IN4	Single-ended input pair	Supports CMOS/SSTL/HSTL; 5–350 MHz; VIH = 0.7×VDD, VIL = 0.3×VDD
CLK0A, CLK0B	Differential output #0	Configurable format/voltage; supports LVPECL/LVDS/HCSL/CML up to 710 MHz
CLK1A, CLK1B	Differential output #1	Independent frequency/phase/format; same capabilities as CLK0A/B
CLK2A, CLK2B	Differential output #2	Programmable spread spectrum; phase adjust <20 ps step resolution
CLK3A, CLK3B	Differential output #3	Supports zero-delay mode via external feedback path (fb pin)
SCL, SDA	I²C interface	Standard SMBus-compatible bus; 400 kHz max; supports ClockBuilder Pro programming
INTR	Interrupt output	Open-drain alarm signal for loss-of-lock or loss-of-signal events
VDD	Core supply	1.8/2.5/3.3 V ±10%; 45 mA typical current draw at 100 MHz on all outputs
VDDO0–VDDO3	Output buffer supplies	Independent 1.5/1.8/2.5/3.3 V per output group; enables mixed-voltage system interfacing

Key Features

Feature	Design Value
MultiSynth™ synthesis	Four independent fractional-N synthesizers enabling any-frequency generation (0.16–710 MHz) with 0 ppm error on all outputs
PCIe Gen 4 compliance	0.15–0.45 ps RMS jitter in Common Clock mode; validated per PCI-SIG Base Spec 4.0 rev 0.5
Per-output voltage control	Each of four output banks supports selectable 1.5/1.8/2.5/3.3 V VDDO, enabling direct interface to mixed-voltage FPGAs and processors
Glitchless frequency tuning	Hardware-supported frequency increment/decrement (1 ppm steps) with ≤667 ns update time, no output interruption
Programmable spread spectrum	Configurable on any output: 0.5–5.0% spread depth, 33–63 kHz modulation rate, 5–350 MHz frequency range
Zero-delay mode	External feedback path (fb pin) allows synchronous alignment of output clocks to input reference with sub-ns latency

Applications

Ethernet Switch Timing	PCIe Gen 4 Server Clocking
Use Scenario: High-density 10/25/100 GbE switch fabric requiring low-jitter, multi-frequency clocks for SerDes lanes, MAC, and CPU interfaces. IC Role / Device Role / Timing Role: Quad clock generator providing four independent, jitter-clean clocks (e.g., 156.25 MHz, 312.5 MHz, 625 MHz, 1.25 GHz divided) with precise phase alignment. Use Value: Meets IEEE 802.3bj/ck jitter budgets; eliminates need for multiple discrete oscillators; reduces board space and BOM count.	Use Scenario: Dual-CPU server motherboard with PCIe Gen 4 x16 slots, NVMe storage, and PLX switches demanding strict common-clock jitter compliance. IC Role / Device Role / Timing Role: PCIe Common Clock source delivering 100 MHz reference to root complex, endpoints, and switches with ≤0.45 ps RMS jitter. Use Value: Passes Intel Clock Jitter Tool v1.6.4 validation; supports SRNS mode for Gen 3; enables single-device clock tree simplification.
Broadcast Video Synchronization	FPGA-Based Test Equipment
Use Scenario: SMPTE ST 2082/2110 video-over-IP gateway requiring frame-accurate 27 MHz, 74.25 MHz, and 148.5 MHz clocks with <±1 ns skew. IC Role / Device Role / Timing Role: Multi-format clock synthesizer generating three synchronized video clocks with programmable phase offsets. Use Value: Achieves <100 ps output-to-output skew; supports HCSL/LVDS/CMOS outputs for different PHY layers; eliminates external delay lines.	Use Scenario: High-speed digital pattern generator using Xilinx UltraScale+ FPGA needing four precisely timed clocks (e.g., 200 MHz system, 400 MHz DDR, 800 MHz SerDes, 1 GHz sampling). IC Role / Device Role / Timing Role: Configurable clock source with independent frequency/phase/voltage per bank for heterogeneous FPGA clock domains. Use Value: Enables glitchless frequency switching during test sequence changes; supports 1.8 V and 2.5 V I/O banks simultaneously.

Ethernet Switch Timing

PCIe Gen 4 Server Clocking

Use Scenario: High-density 10/25/100 GbE switch fabric requiring low-jitter, multi-frequency clocks for SerDes lanes, MAC, and CPU interfaces.

IC Role / Device Role / Timing Role: Quad clock generator providing four independent, jitter-clean clocks (e.g., 156.25 MHz, 312.5 MHz, 625 MHz, 1.25 GHz divided) with precise phase alignment.

Use Value: Meets IEEE 802.3bj/ck jitter budgets; eliminates need for multiple discrete oscillators; reduces board space and BOM count.

Use Scenario: Dual-CPU server motherboard with PCIe Gen 4 x16 slots, NVMe storage, and PLX switches demanding strict common-clock jitter compliance.

IC Role / Device Role / Timing Role: PCIe Common Clock source delivering 100 MHz reference to root complex, endpoints, and switches with ≤0.45 ps RMS jitter.

Use Value: Passes Intel Clock Jitter Tool v1.6.4 validation; supports SRNS mode for Gen 3; enables single-device clock tree simplification.

Broadcast Video Synchronization

FPGA-Based Test Equipment

Use Scenario: SMPTE ST 2082/2110 video-over-IP gateway requiring frame-accurate 27 MHz, 74.25 MHz, and 148.5 MHz clocks with <±1 ns skew.

IC Role / Device Role / Timing Role: Multi-format clock synthesizer generating three synchronized video clocks with programmable phase offsets.

Use Value: Achieves <100 ps output-to-output skew; supports HCSL/LVDS/CMOS outputs for different PHY layers; eliminates external delay lines.

Use Scenario: High-speed digital pattern generator using Xilinx UltraScale+ FPGA needing four precisely timed clocks (e.g., 200 MHz system, 400 MHz DDR, 800 MHz SerDes, 1 GHz sampling).

IC Role / Device Role / Timing Role: Configurable clock source with independent frequency/phase/voltage per bank for heterogeneous FPGA clock domains.

Use Value: Enables glitchless frequency switching during test sequence changes; supports 1.8 V and 2.5 V I/O banks simultaneously.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5338A-B04337-GM	Same silicon, factory-programmed OTP variant; fixed configuration stored in NVM; no I²C reprogramming required at power-up	Suitable for volume production where clock frequencies are static; eliminates boot-time I²C initialization	Select when deterministic startup behavior and reduced firmware dependency are critical
LMK04832RHAT	Two PLLs + 14 outputs; higher integration but larger 48-QFN package; 0.18 ps RMS jitter; supports JESD204B	Better suited for RF/data converter timing with ultra-low jitter and multi-device synchronization	Select when >4 outputs or JESD204B deterministic latency is required; not drop-in compatible

Compared with Si5338A-B04337-GM, SI5338N-B04337-GMR offers field-programmability and dynamic reconfiguration, while LMK04832RHAT provides greater output count and lower jitter at the cost of size and complexity-making SI5338N-B04337-GMR optimal for compact, flexible, PCIe/Ethernet timing where four outputs suffice.

Availability

SI5338N-B04337-GMR is available at Aetrix Electronics and suitable for Ethernet switch/router, PCIe Gen 1–4 server platforms, and broadcast video timing applications requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for SI5338N-B04337-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5338 product line delivers programmable, low-jitter clock generation for high-speed serial interfaces-including PCIe, Ethernet, and video-designed to replace multiple fixed-frequency oscillators with a single configurable IC.

FAQ

What is the maximum output frequency supported by SI5338N-B04337-GMR?

The SI5338N-B04337-GMR supports up to 710 MHz on LVPECL/LVDS/CML outputs, 350 MHz on SSTL/HSTL, 250 MHz on HCSL, and 200 MHz on CMOS. Above 350 MHz, only two unique frequencies may be generated simultaneously (Fvco/4 and Fvco/6), as defined by the MultiSynth™ VCO architecture.

Does SI5338N-B04337-GMR support PCIe Gen 4 Common Clock compliance?

Yes, SI5338N-B04337-GMR meets PCIe Gen 4 Common Clock jitter requirements with ≤0.45 ps RMS (1.5–50 MHz band) when configured per Skyworks AN562 guidelines and measured using the Intel Clock Jitter Tool v1.6.4. It also satisfies Gen 3 SRNS and Gen 1/2 specifications.

How is the SI5338N-B04337-GMR programmed and configured?

SI5338N-B04337-GMR is programmed via its I²C/SMBus interface using Skyworks' ClockBuilder Pro software, which generates register maps and configuration files. Configuration can be loaded at boot via EEPROM or applied dynamically during operation without interrupting outputs.

Can SI5338N-B04337-GMR generate different output voltages on each channel?

Yes, SI5338N-B04337-GMR provides four independent VDDO supply pins (VDDO0–VDDO3), each configurable for 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This allows simultaneous LVDS (2.5 V), HCSL (1.8 V), and CMOS (3.3 V) outputs without level-shifting components.

What is the thermal performance of SI5338N-B04337-GMR in continuous operation?

SI5338N-B04337-GMR has a junction-to-ambient thermal resistance (θJA) of 37 °C/W in still air. At 45 mA core current and full output load, junction temperature rise remains within safe limits up to +85 °C ambient, provided the exposed thermal pad is properly soldered to a ≥1 cm² copper pour.

SI5338N-B04337-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338N-B04337-GMR FAQ

1.How can I place an order for SI5338N-B04337-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338N-B04337-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338N-B04337-GMR reliable?

The price and inventory of SI5338N-B04337-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338N-B04337-GMR is usually 5 days.

3.What payment methods are accepted for SI5338N-B04337-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338N-B04337-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338N-B04337-GMR?

SI5338N-B04337-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338N-B04337-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338N-B04337-GMR?

For technical support, including SI5338N-B04337-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338N-B04337-GMR requirements.

6.How does Aetrix verify that SI5338N-B04337-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338N-B04337-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338N-B04337-GMR meets industry standards.

7.What is the process for return or replacement of SI5338N-B04337-GMR?

All SI5338N-B04337-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338N-B04337-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338N-B04337-GMR part is unused and in its original packaging.

Return procedure for SI5338N-B04337-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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