Skyworks Solutions Inc. SI5338N-B04374-GM
- Part No.:
- SI5338N-B04374-GM
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Application Specific Clock/Timing
- Package:
- 24-VFQFN Exposed Pad
- Datasheet:
-
SI5338N-B04374-GM.pdf
- Description:
- I2C CONTROL, 4-OUTPUT, ANY FREQU
- Quantity:
- Payment:

- Shipping:

Inventory:2,140
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SI5338N-B04374-GM from Skyworks Solutions is an I²C-programmable quad clock generator IC with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation across –40 to +85 °C in a 4 × 4 mm 24-QFN package. It replaces up to four crystal oscillators in high-speed serial interface timing applications.
For engineers reviewing the SI5338N-B04374-GM datasheet, SI5338N-B04374-GM pinout, SI5338N-B04374-GM application, or SI5338N-B04374-GM equivalent, key selection considerations include its MultiSynth™-based any-frequency synthesis (0.16–710 MHz per output), independent output voltage control (1.5/1.8/2.5/3.3 V), spread-spectrum capability (0.5–5.0% down-spread), and I²C/SMBus programmability with ClockBuilder Pro support.
Technical Context
The SI5338N-B04374-GM implements a two-stage PLL architecture: a high-stability reference stage (with crystal or external clock input) followed by four independent MultiSynth™ fractional-N synthesis paths. Each path supports integer or fractional mode operation, enabling precise frequency generation without multiplication-induced jitter accumulation.
Its output stage provides per-driver configurability for LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats, independent VDDO supply per bank (1.5–3.3 V), and features including glitchless frequency increment/decrement (1 ppm steps), sub-20 ps phase adjustment, and loss-of-lock/loss-of-signal alarms - all managed via a register-mapped I²C interface.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Count & Type | Four independent outputs; each configurable as differential (LVPECL/LVDS/HCSL/CML) or single-ended (CMOS/SSTL/HSTL) |
| Frequency Range | 0.16–710 MHz per output; supports >350 MHz on up to two outputs simultaneously (Fvco/4 and Fvco/6) |
| Phase Jitter (RMS) | 0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 3 SRNS (0.11–0.32 ps RMS) and Gen 4 common clock (0.15–0.45 ps RMS) |
| Input Flexibility | Supports 8–30 MHz crystal, 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL, or 5–710 MHz differential reference |
| Supply & Power | 1.8/2.5/3.3 V core (±10%); 1.4–3.63 V per output bank; 45 mA typical core current at 100 MHz on all outputs |
| Operating Temperature | –40 to +85 °C ambient; qualified per industrial temperature grade requirements |
| Package | 24-pin QFN, 4 × 4 mm, 0.5 mm pitch, exposed thermal pad |
Pinout & Package
SI5338N-B04374-GM uses a 24-lead QFN package (4 × 4 mm, 0.5 mm pitch) with an exposed thermal pad. Pin assignments are fixed per the Si5338 family and validated for this variant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN1, IN2 | Differential reference input pair | Accepts 5–710 MHz AC-coupled differential clock; requires external 100 Ω termination |
| IN3, IN4 | Single-ended reference inputs | Support 5–200 MHz CMOS-level clocks; VIH = 0.7×VDD, VIL = 0.3×VDD |
| CLK0A, CLK0B to CLK3A, CLK3B | Differential output pairs | Four independent differential outputs; each configurable for LVPECL/LVDS/HCSL/CML format and voltage |
| VDDO0–VDDO3 | Output buffer supply pins | Independent 1.5/1.8/2.5/3.3 V supplies per output bank; enables mixed-voltage system interfacing |
| VDD | Core supply | 1.8/2.5/3.3 V ±10% core power; PSRR optimized for low-noise clock generation |
| SCL, SDA | I²C/SMBus interface | Standard 100/400 kHz I²C bus; supports ClockBuilder Pro programming and runtime reconfiguration |
| INTR | Interrupt output | Open-drain status indicator for loss-of-lock (LOL) and loss-of-signal (LOS) events |
Key Features
| Feature | Design Value |
|---|---|
| MultiSynth™ Any-Frequency Synthesis | Generates four independent, zero-ppm-accurate output frequencies from a single reference - eliminates need for multiple crystals or discrete synthesizers |
| PCIe Gen 1–4 Timing Compliance | Fully compliant with PCIe Common Clock (Gen 1–4) and Gen 3 Separate Reference No Spread (SRNS) jitter specifications |
| Per-Output Voltage & Format Control | Each of four output banks supports independent VDDO (1.5/1.8/2.5/3.3 V) and signal format (LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL) |
| Glitchless Frequency Tuning | Real-time frequency increment/decrement in 1 ppm steps without output interruption - critical for dynamic rate adaptation |
| Programmable Spread Spectrum | Configurable down-spread (0.5–5.0%) and modulation rate (33–63 kHz) on any output to reduce EMI in noise-sensitive systems |
| External Feedback Zero-Delay Mode | Enables zero-delay clock buffering configuration using external feedback path - preserves input timing integrity |
Applications
| PCIe Gen 4 Switch Timing | Ethernet Switch/Routing |
|---|---|
Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe Gen 4 switch ASICs in a data center fabric card. IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent, low-jitter HCSL clocks meeting PCIe Gen 4 common clock jitter limits (≤0.45 ps RMS). Use Value: Eliminates four discrete oscillators while maintaining <0.7 ps RMS jitter and supporting per-port spread-spectrum control to meet EMI Class B requirements. |
Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1 GbE/10 GbE PHYs and packet processors in a carrier-grade Ethernet switch. IC Role / Device Role / Timing Role: Configurable clock source with mixed-output formats (LVDS for PHYs, CMOS for processors) and independent voltage rails. Use Value: Reduces BOM count and layout area versus discrete solutions; enables single-reference synchronization across multi-rate interfaces. |
| Broadcast Video Timing | FPGA Processor Clocking |
Use Scenario: Delivering SMPTE ST 2082 (27 Gbps) pixel clock and ancillary timing signals (e.g., 74.25 MHz, 148.5 MHz) to video encoder/decoder FPGAs in 4K/8K broadcast equipment. IC Role / Device Role / Timing Role: High-precision, low-phase-noise clock synthesizer generating multiple video-standard frequencies from one crystal reference. Use Value: Achieves <10 ps pk-pk period jitter required for 27 Gbps serial links; avoids jitter accumulation from cascaded PLLs. |
Use Scenario: Supplying 300 MHz system clock, 200 MHz DDR4 memory clock, and 100 MHz peripheral interface clock to a Xilinx Versal FPGA in an industrial AI edge node. IC Role / Device Role / Timing Role: Programmable quad clock generator with independent output voltage control (1.8 V for DDR4, 1.0 V for FPGA core via level-shifter, 3.3 V for peripherals). Use Value: Enables single-chip timing solution for heterogeneous voltage domains; supports runtime reconfiguration via I²C during FPGA bitstream updates. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad clock generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5332A-D06989-GM | Higher integration: includes integrated LDOs, enhanced PCIe Gen 5/6 jitter performance (0.08 ps RMS), and dual-loop architecture | Targeted at next-gen server and AI accelerator platforms requiring Gen 5+ compliance and lower power | Choose when upgrading beyond Gen 4 or requiring integrated power regulation; not drop-in compatible due to different pinout and register map |
| ICS8430I-01T | Fixed-frequency, non-programmable quad LVDS clock generator; no I²C interface; 1.2 ps RMS jitter; 100–700 MHz range | Used in cost-sensitive, static-clocking applications where frequency flexibility is unnecessary | Choose only for simple, unchanging clock trees; lacks any-frequency synthesis, spread spectrum, or voltage/format configurability of SI5338N-B04374-GM |
Compared with Si5332A-D06989-GM and ICS8430I-01T, the SI5338N-B04374-GM delivers optimal balance of programmability, PCIe Gen 4 readiness, and industrial temperature support - making it ideal for field-upgradable telecom, networking, and broadcast systems where design longevity and configuration flexibility are critical.
Availability
SI5338N-B04374-GM is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, Ethernet switching/routing, and broadcast video timing applications requiring stable component supply, long-term lifecycle assurance, and full traceability.
Supply support for SI5338N-B04374-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and industrial markets.
The Si5338 product line was designed specifically for high-performance, software-configurable clock generation in multi-protocol serial interface systems - addressing PCIe, Ethernet, Fibre Channel, and broadcast video timing requirements with single-chip flexibility.
FAQ
What is the maximum output frequency supported by the SI5338N-B04374-GM?
The SI5338N-B04374-GM supports up to 710 MHz on LVPECL/LVDS/CML outputs, 250 MHz on HCSL, and 200 MHz on CMOS. However, only two unique frequencies above 350 MHz can be generated simultaneously - specifically Fvco/4 and Fvco/6 - as defined by the internal VCO architecture and MultiSynth™ constraints.
Does the SI5338N-B04374-GM support PCIe Gen 4 Common Clock compliance?
Yes, the SI5338N-B04374-GM meets PCIe Gen 4 Common Clock jitter requirements with ≤0.45 ps RMS (1.5 MHz–50 MHz band) when configured per Skyworks' recommended settings, including PLL bandwidth of 2–4 MHz and CDR = 10 MHz. This is verified in Table 12 of the official datasheet Rev. 1.6.
Can the SI5338N-B04374-GM generate different output voltages on separate pins?
Yes, the SI5338N-B04374-GM provides four independent VDDO supply pins (VDDO0–VDDO3), each configurable for 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This allows simultaneous LVDS (2.5 V), HCSL (1.8 V), and CMOS (3.3 V) outputs - essential for interfacing with mixed-voltage SoCs and FPGAs.
How is the SI5338N-B04374-GM programmed, and is external hardware required?
The SI5338N-B04374-GM is programmed via its I²C/SMBus interface (SCL/SDA pins) using Skyworks' ClockBuilder Pro software. No external programmer is needed - configuration is performed through a standard USB-to-I²C adapter or evaluation board. Factory-programmed OTP NVM retains settings across power cycles.
What is the thermal performance of the SI5338N-B04374-GM in continuous operation?
The SI5338N-B04374-GM has a junction-to-ambient thermal resistance (θJA) of 37 °C/W under still-air conditions. With typical core power dissipation of ~150 mW (45 mA @ 3.3 V), junction temperature rise remains within safe limits (<3°C rise) - enabling reliable operation at full load across the –40 to +85 °C industrial range.
SI5338N-B04374-GM Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- MultiSynth™
- Package/Case:
- 24-VFQFN Exposed Pad
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- PLL:
- -
- Main Purpose:
- -
- Input:
- -
- Output:
- -
- Number of Circuits:
- -
- Ratio - Input:Output:
- -
- Differential - Input:Output:
- -
- Frequency - Max:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 24-QFN (4x4)
SI5338N-B04374-GM FAQ
1.How can I place an order for SI5338N-B04374-GM through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5338N-B04374-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5338N-B04374-GM reliable?
The price and inventory of SI5338N-B04374-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338N-B04374-GM is usually 5 days.
3.What payment methods are accepted for SI5338N-B04374-GM?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338N-B04374-GM transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5338N-B04374-GM?
SI5338N-B04374-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5338N-B04374-GM order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5338N-B04374-GM?
For technical support, including SI5338N-B04374-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338N-B04374-GM requirements.
6.How does Aetrix verify that SI5338N-B04374-GM is sourced from the original manufacturer or authorized distributors?
All SI5338N-B04374-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338N-B04374-GM meets industry standards.
7.What is the process for return or replacement of SI5338N-B04374-GM?
All SI5338N-B04374-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338N-B04374-GM, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5338N-B04374-GM part is unused and in its original packaging.
Return procedure for SI5338N-B04374-GM:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SI5338N-B04374-GM Tags

-
LMK00334RTVRQ1
Texas Instruments
.jpg)
-
DSC557-0344FI0T
Microchip Technology

-
9FGV0241AKILFT
Renesas

-
9DBL0452CKILFT
Renesas
.jpg)
-
DSC557-0344FL1T
Microchip Technology
-
RC19008AGND#KB0
Renesas
-
RC19008AGND#BB0
Renesas

-
9DB403DGILFT
Renesas

-
9DB233AGILFT
Renesas

-
9DB803DGILFT
Renesas

-
9FGL0851DKILFT
Renesas
-
AB-557-03-HCHC-F-L-C-T
Abracon LLC
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

