Skyworks Solutions Inc. SI5338N-B04781-GMR
- Part No.:
- SI5338N-B04781-GMR
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Application Specific Clock/Timing
- Package:
- 24-VFQFN Exposed Pad
- Datasheet:
-
SI5338N-B04781-GMR.pdf
- Description:
- I2C CONTROL, 4-OUTPUT, ANY FREQU
- Quantity:
- Payment:

- Shipping:

Inventory:4,171
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Product details
Overview
SI5338N-B04781-GMR from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation across –40 to +85 °C. It replaces up to four crystal oscillators in Ethernet switch/router, PCIe, and FPGA clocking systems.
For engineers reviewing the SI5338N-B04781-GMR datasheet, SI5338N-B04781-GMR pinout, SI5338N-B04781-GMR application, or SI5338N-B04781-GMR equivalent, key selection factors include its MultiSynth™-based any-frequency synthesis (0.16–710 MHz per output), independent output voltage support (1.5/1.8/2.5/3.3 V), spread-spectrum capability (0.5–5.0% down-spread), and 24-pin 4×4 mm QFN package with I²C/SMBus interface.
Technical Context
The SI5338N-B04781-GMR implements a two-stage PLL architecture: a high-stability reference stage (with crystal or external clock input) feeding a fractional-N MultiSynth™ synthesis stage per output. Each of the four output drivers supports independent frequency, format (LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL), voltage, phase offset (±45 ns), and spread-spectrum modulation.
It features loss-of-lock and loss-of-signal detection, programmable initial phase offset (<20 ps step resolution), glitchless frequency increment/decrement in 1 ppm steps, and external feedback mode for zero-delay operation. Core supply operates at 1.8/2.5/3.3 V with 45 mA typical current draw.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Phase Jitter (RMS) | 0.7 ps - meets PCIe Gen 3 SRNS and GbE jitter requirements with differential outputs |
| Output Frequency Range | 0.16–710 MHz - supports LVPECL/LVDS (≤710 MHz), HCSL (≤250 MHz), CMOS (≤200 MHz), SSTL/HSTL (≤350 MHz) |
| Input Reference Support | Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz) - enables flexible system clock sourcing |
| Supply Voltages | Core: 1.8/2.5/3.3 V; Output buffers: independently configurable 1.5/1.8/2.5/3.3 V - allows mixed-voltage timing domain interfacing |
| Package | 24-pin QFN, 4 × 4 mm - space-efficient footprint compatible with high-density PCB layouts |
| Operating Temperature | –40 to +85 °C - qualified for industrial and telecom line card environments |
| I²C Interface | SMBus-compatible, 100 kHz/400 kHz - enables configuration and monitoring without dedicated programming hardware |
Pinout & Package
SI5338N-B04781-GMR is housed in a 24-lead, 4 × 4 mm QFN package with exposed thermal pad. Pin assignments follow the standard Si5338 top-view layout: dual differential inputs (IN1/IN2, IN5/IN6), two single-ended inputs (IN3, IN4), four differential output pairs (CLK0A/B through CLK3A/B), six VDDOx power pins (VDDO0–VDDO3), core VDD, SCL/SDA, INTR, and ground/pad connections.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN1 / IN2 | Differential reference input pair | Accepts 5–710 MHz AC-coupled differential clock; requires external 100 Ω termination |
| CLK0A / CLK0B | Differential output pair 0 | Configurable format/voltage/frequency; supports LVPECL/LVDS/HCSL/CML/SSTL |
| VDDO0 | Output buffer supply for CLK0A/B | Independent 1.5/1.8/2.5/3.3 V rail - isolates output noise from core logic |
| SCL / SDA | I²C serial interface | Standard SMBus-compatible control bus; enables full device configuration and status readback |
| INTR | Interrupt output | Open-drain signal indicating loss-of-lock, loss-of-signal, or other fault conditions |
Key Features
| Feature | Design Value |
|---|---|
| MultiSynth™ synthesis per output | Enables true zero-ppm frequency accuracy on all four outputs simultaneously, eliminating need for multiple crystals |
| Independent output voltage per driver | Allows direct interfacing with mixed-voltage devices (e.g., 1.8 V FPGA core + 3.3 V legacy peripheral) without level shifters |
| Programmable spread spectrum | Reduces EMI by enabling user-defined down-spread (0.5–5.0%) and modulation rate (33–63 kHz) on any output |
| Glitchless frequency adjustment | Supports real-time, sub-ppm frequency tuning via PINC/FDEC pins without output interruption - critical for dynamic clock scaling |
| External feedback mode | Permits zero-delay clock distribution by routing one output back as feedback, synchronizing output phase to input |
Applications
| PCIe Gen 4 System Clocking | Ethernet Switch Timing |
|---|---|
Use Scenario: Providing synchronized 100 MHz common clock to multiple PCIe Gen 4 endpoints and root complex in a server motherboard. IC Role / Device Role / Timing Role: Quad-output clock generator delivering low-jitter, SRNS-compliant reference clocks with independent skew control. Use Value: Meets PCIe Gen 4 total jitter limit of ≤0.45 ps RMS while enabling single-device consolidation of four discrete oscillators. |
Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10 GbE PHYs, packet processors, and SerDes in a modular switch fabric. IC Role / Device Role / Timing Role: Any-frequency synthesizer with independent output formatting and voltage control per port. Use Value: Eliminates custom crystal sourcing and reduces BOM count by generating all required frequencies from one 25 MHz reference. |
| FPGA/ASIC Clock Domain Crossing | Broadcast Video Synchronization |
Use Scenario: Supplying 200 MHz system clock, 100 MHz DDR3 interface clock, 50 MHz test clock, and 10 MHz debug clock to a multi-domain SoC design. IC Role / Device Role / Timing Role: Configurable quad clock source with independent phase offset and format per output. Use Value: Enables precise inter-clock alignment (±20 ps step resolution) and eliminates external delay lines or PLLs for domain synchronization. |
Use Scenario: Delivering SMPTE ST 2059-2–compliant 27 MHz, 74.25 MHz, and 148.5 MHz reference clocks to video encoders, decoders, and genlock circuits in broadcast infrastructure. IC Role / Device Role / Timing Role: Low-phase-jitter clock generator supporting exact frequency synthesis and spread-spectrum EMI reduction. Use Value: Achieves <0.7 ps RMS jitter required for 4K/8K video transport while meeting FCC Class A radiated emissions limits via programmable SSC. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad clock generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5332A-D06889-GM | Higher integration: 8 outputs, integrated EEPROM, lower jitter (0.35 ps RMS), supports JESD204B deterministic latency | Targeted at high-channel-count data converter systems requiring sub-ps jitter and deterministic phase alignment | Choose when >4 outputs, tighter jitter, or JESD204B compliance are required; not pin-compatible |
| ICS8430I-01T | Fixed-frequency quad LVDS generator (no I²C programming); 1.2 ps RMS jitter; 3.3 V only; no spread spectrum | Used in cost-sensitive, static-clock applications where reconfiguration is unnecessary | Choose for simple, low-cost replacement of fixed-frequency oscillators; lacks frequency flexibility and voltage configurability |
Compared with SI5338N-B04781-GMR, Si5332A-D06889-GM offers higher channel count and lower jitter but requires board redesign, while ICS8430I-01T provides simpler fixed-clock operation at the expense of programmability and multi-voltage support.
Availability
SI5338N-B04781-GMR is available at Aetrix Electronics and suitable for Ethernet switch/router, PCIe Gen 4 platform development, and FPGA-based industrial control systems requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.
Supply support for SI5338N-B04781-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for communications infrastructure, automotive, and industrial markets.
The Si5338 product line delivers programmable, low-jitter clock generation for high-speed digital systems including PCIe, Ethernet, and broadcast video, emphasizing flexibility, integration, and EMI reduction through spread-spectrum capability.
FAQ
What is the maximum output frequency supported by SI5338N-B04781-GMR in LVPECL format?
The SI5338N-B04781-GMR supports LVPECL output frequencies up to 710 MHz, as confirmed in Table 6 of the datasheet. This capability applies when using differential outputs with appropriate termination and load conditions, and is validated for jitter performance under specified operating conditions.
Does SI5338N-B04781-GMR support PCIe Gen 4 Common Clock compliance?
Yes, SI5338N-B04781-GMR meets PCIe Gen 4 Common Clock RMS jitter requirements (≤0.45 ps RMS) as specified in Table 12 of the datasheet. It achieves this with differential outputs (e.g., HCSL) and proper reference clock conditioning, and is explicitly listed among compliant applications in the product description.
Can SI5338N-B04781-GMR generate different output voltages on each driver?
Yes, SI5338N-B04781-GMR supports independent output buffer supply voltages (VDDO0–VDDO3) selectable per driver from 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This enables simultaneous interfacing with mixed-voltage components such as 1.8 V FPGAs and 3.3 V legacy peripherals without external level shifters.
Is an external crystal required for SI5338N-B04781-GMR operation?
No, SI5338N-B04781-GMR accepts multiple reference sources: an external 8–30 MHz crystal (connected to IN1/IN2), or external CMOS/SSTL/HSTL/differential clocks (5–710 MHz). Crystal use is optional and depends on system-level timing stability and jitter requirements.
What software tools are available to configure SI5338N-B04781-GMR?
Skyworks ClockBuilder Pro is the official configuration tool for SI5338N-B04781-GMR. It enables GUI-based frequency planning, output format assignment, spread-spectrum setup, and register file generation. The tool also supports validation against PCIe, GbE, and SONET jitter masks and exports configuration files for production programming.
SI5338N-B04781-GMR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- MultiSynth™
- Package/Case:
- 24-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- PLL:
- -
- Main Purpose:
- -
- Input:
- -
- Output:
- -
- Number of Circuits:
- -
- Ratio - Input:Output:
- -
- Differential - Input:Output:
- -
- Frequency - Max:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 24-QFN (4x4)
SI5338N-B04781-GMR FAQ
1.How can I place an order for SI5338N-B04781-GMR through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5338N-B04781-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5338N-B04781-GMR reliable?
The price and inventory of SI5338N-B04781-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338N-B04781-GMR is usually 5 days.
3.What payment methods are accepted for SI5338N-B04781-GMR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338N-B04781-GMR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5338N-B04781-GMR?
SI5338N-B04781-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5338N-B04781-GMR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5338N-B04781-GMR?
For technical support, including SI5338N-B04781-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338N-B04781-GMR requirements.
6.How does Aetrix verify that SI5338N-B04781-GMR is sourced from the original manufacturer or authorized distributors?
All SI5338N-B04781-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338N-B04781-GMR meets industry standards.
7.What is the process for return or replacement of SI5338N-B04781-GMR?
All SI5338N-B04781-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338N-B04781-GMR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5338N-B04781-GMR part is unused and in its original packaging.
Return procedure for SI5338N-B04781-GMR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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