Skyworks Solutions Inc. SI5338N-B04890-GM
- Part No.:
- SI5338N-B04890-GM
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Application Specific Clock/Timing
- Package:
- 24-VFQFN Exposed Pad
- Datasheet:
-
SI5338N-B04890-GM.pdf
- Description:
- I2C CONTROL, 4-OUTPUT, ANY FREQU
- Quantity:
- Payment:

- Shipping:

Inventory:3,043
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SI5338N-B04890-GM from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation from 1.8/2.5/3.3 V core supply in a 4 × 4 mm 24-QFN package. It replaces up to four crystal oscillators in high-speed serial interface timing applications.
For engineers reviewing the SI5338N-B04890-GM datasheet, SI5338N-B04890-GM pinout, SI5338N-B04890-GM application, or SI5338N-B04890-GM equivalent, key selection criteria include PCIe Gen 4 jitter compliance (0.15–0.45 ps RMS), independent output voltage per driver (1.5/1.8/2.5/3.3 V), MultiSynth™ frequency synthesis resolution (1 ppb), spread-spectrum control (0.5–5.0% spread, 33–63 kHz modulation), and loss-of-lock/loss-of-signal alarm support.
Technical Context
The SI5338N-B04890-GM implements a two-stage PLL architecture: a high-stability reference stage (with programmable R-divider) feeding a fractional-N MultiSynth™ VCO stage (with M/N dividers), enabling any-frequency synthesis from 0.16 MHz to 710 MHz across four outputs. Each output path includes independent P-divider, format selection (LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL), and output supply rail (VDDO0–VDDO3).
It supports flexible reference inputs - external crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), or differential (5–710 MHz) - and features glitchless frequency increment/decrement (1 ppm steps), phase adjustment (<20 ps step accuracy), and external feedback for zero-delay mode. The device integrates one-time-programmable (OTP) NVM for factory configuration.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Phase Jitter (RMS) | 0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 4 common clock jitter spec (≤0.45 ps RMS) |
| Output Frequency Range | 0.16–710 MHz per channel; supports LVPECL/LVDS up to 710 MHz, HCSL up to 250 MHz, CMOS up to 200 MHz |
| Synthesis Resolution | 1 ppb; enables true zero-ppm frequency accuracy on all outputs via fractional-N MultiSynth™ |
| Input Reference Options | Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz) |
| Supply Voltages | Core: 1.8/2.5/3.3 V ±10%; Output buffers: independently configurable 1.5/1.8/2.5/3.3 V per VDDOx rail |
| Package | 24-pin QFN, 4 × 4 mm, 0.5 mm pitch; RoHS-compliant, –40 to +85 °C operating range |
| PCIe Compliance | Gen 1/2/3/4 Common Clock; Gen 3 SRNS; additive jitter <0.32 ps RMS (SRNS mode) |
Pinout & Package
SI5338N-B04890-GM uses a 24-lead QFN package (4 × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are defined per Skyworks Rev. 1.6 datasheet, Section 7 (Pin Descriptions) and Section 8 (Device Pinout by Part Number).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN1, IN2, IN5, IN6 | Differential input pairs | Accept AC-coupled differential clocks up to 710 MHz; require external 100 Ω termination |
| IN3, IN4 | Single-ended input pins | Support CMOS/SSTL/HSTL inputs (5–350 MHz); VIH = 0.7×VDD, VIL = 0.3×VDD |
| CLK0A–CLK3B | Differential output pairs (4 channels) | Each pair supports LVPECL/LVDS/HCSL/CML; individually format- and voltage-configurable |
| VDDO0–VDDO3 | Output buffer supply rails | Independent 1.5/1.8/2.5/3.3 V supplies per output channel; decoupling required per rail |
| VDD | Core supply | Single 1.8/2.5/3.3 V supply for PLL, logic, and memory; PSRR optimized |
| SCL, SDA | I²C/SMBus interface | Standard 100/400 kHz operation; supports ClockBuilder Pro programming |
| INTR | Interrupt output | Open-drain status indicator for loss-of-lock (LOL) and loss-of-signal (LOS) |
Key Features
| Feature | Design Value |
|---|---|
| Independent output voltage per driver | Enables mixed-voltage system clocking (e.g., 1.8 V FPGA core + 3.3 V legacy peripheral) without level shifters |
| Programmable initial phase offset | ±45 ns adjustment per output; critical for deterministic skew control in multi-lane SerDes (e.g., PCIe x16, 10GbE) |
| Glitchless frequency increment/decrement | 1 ppm step size with <667 ns update time; supports dynamic frequency scaling in adaptive systems |
| Spread spectrum on any output | Configurable 0.5–5.0% down-spread at 33–63 kHz; reduces EMI peak emissions without affecting timing margins |
| External feedback mode | Supports zero-delay buffer operation; eliminates propagation delay between input and output clocks |
Applications
| PCIe Gen 4 Switch Timing | Ethernet Switch Clocking |
|---|---|
Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe Gen 4 switch ASICs in a data center top-of-rack switch. IC Role / Device Role / Timing Role: Quad-output clock generator delivering four low-jitter, phase-aligned clocks meeting PCIe Gen 4 Common Clock jitter spec (≤0.45 ps RMS). Use Value: Eliminates need for four discrete oscillators; ensures deterministic inter-lane skew <100 ps across all switch ports. | Use Scenario: Generating 156.25 MHz and 312.5 MHz clocks for 10GbE/25GbE PHYs and MACs in carrier-grade Ethernet switches. IC Role / Device Role / Timing Role: Any-frequency synthesizer producing precise Ethernet line rates with <0.7 ps RMS jitter (GbE random jitter spec). Use Value: Enables single-device clock tree for multi-rate PHYs; avoids jitter accumulation from cascaded PLLs. |
| Broadcast Video Sync Generator | FPGA-Based Video Processing |
Use Scenario: Deriving SMPTE ST 2082 (12G-SDI) 594 MHz and ST 2081 (6G-SDI) 297 MHz clocks from a 27 MHz master reference in broadcast video equipment. IC Role / Device Role / Timing Role: High-frequency differential clock generator supporting LVPECL outputs up to 710 MHz with sub-ps jitter. Use Value: Meets SMPTE jitter limits (<0.3 UI) for uncompressed 4K/8K video transport over coaxial cable. | Use Scenario: Supplying 300 MHz pixel clock, 150 MHz DDR3 memory clock, and 100 MHz system clock to Xilinx Kintex Ultrascale+ FPGA in real-time video analytics hardware. IC Role / Device Role / Timing Role: Configurable quad clock source with independent voltage rails (1.8 V for FPGA I/O, 1.2 V-compatible via VDDO scaling) and programmable phase alignment. Use Value: Reduces board-level BOM count; enables precise inter-clock phase tuning for timing closure in high-speed video pipelines. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad clock generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5332A-D06880-GM | Higher integration: integrated crystal, lower jitter (0.35 ps RMS), 8 outputs, supports JESD204B deterministic latency | Targeted at JESD204B ADC/DAC synchronization and 5G wireless infrastructure requiring sub-100 fs jitter | Select when deterministic latency, ultra-low jitter, or >4 outputs are required; higher cost and larger 5 × 5 mm package |
| ICS8430I-01T | Fixed-frequency, non-programmable; 4 LVDS outputs; 1.2 ps RMS jitter; no I²C interface or spread spectrum | Used in cost-sensitive, static-clock applications like legacy telecom line cards where frequency agility is unnecessary | Select only for fixed-frequency deployments with no requirement for field reconfiguration or EMI reduction |
Compared with Si5332A-D06880-GM and ICS8430I-01T, the SI5338N-B04890-GM offers optimal balance of field-programmability, PCIe Gen 4 compliance, and compact 4 × 4 mm footprint-making it ideal for space-constrained, multi-standard systems requiring post-production frequency tuning.
Availability
SI5338N-B04890-GM is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, Ethernet switch clocking, broadcast video sync generation, and FPGA-based video processing requiring stable component supply and long-term lifecycle support.
Supply support for SI5338N-B04890-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.
The SI5338 family is designed as a programmable, low-jitter clock generator platform targeting high-speed serial interfaces-including PCIe, Ethernet, Fibre Channel, and broadcast video-where precise frequency synthesis and multi-format output flexibility are essential.
FAQ
What is the maximum output frequency supported by SI5338N-B04890-GM in LVPECL format?
The SI5338N-B04890-GM supports LVPECL outputs up to 710 MHz, as specified in Table 6 of the Skyworks Rev. 1.6 datasheet. This capability enables direct clocking of high-speed SerDes lanes in PCIe Gen 4 and 10G/25G Ethernet PHYs without external frequency multiplication. Operation above 350 MHz is limited to two unique frequencies simultaneously (Fvco/4 and Fvco/6) due to VCO constraints within the MultiSynth™ architecture.
Does SI5338N-B04890-GM support PCIe Gen 4 Separate Reference No Spread (SRNS) mode?
Yes, SI5338N-B04890-GM is compliant with PCIe Gen 4 SRNS requirements, delivering ≤0.32 ps RMS jitter under specified conditions (PLL bandwidth 2–4 MHz, CDR = 10 MHz). This is validated in Table 12 of the datasheet and confirmed by Skyworks' PCIe Clock Jitter Tool. The SI5338N-B04890-GM achieves this using its low-noise MultiSynth™ PLL and optimized loop filter configuration.
Can SI5338N-B04890-GM generate different output voltages on each of its four channels?
Yes, SI5338N-B04890-GM provides independent VDDO0–VDDO3 supply rails, allowing each output channel to be configured for 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This enables simultaneous interfacing with mixed-voltage devices-for example, driving a 1.8 V FPGA I/O bank, a 2.5 V Ethernet PHY, a 3.3 V microcontroller, and a 1.5 V DDR3 memory controller-all from a single SI5338N-B04890-GM device.
How is SI5338N-B04890-GM programmed, and is external non-volatile memory required?
SI5338N-B04890-GM is programmed via its I²C/SMBus interface using Skyworks' ClockBuilder Pro software. Configuration is stored in on-chip one-time-programmable (OTP) memory, eliminating the need for external EEPROM or flash. Factory-programmed units ship with preloaded configurations; field updates are supported via I²C without requiring power-cycle or reset for most parameter changes.
What thermal performance can be expected from SI5338N-B04890-GM in a standard 4-layer PCB layout?
In a standard 4-layer PCB with adequate copper pour and thermal vias under the exposed pad, SI5338N-B04890-GM exhibits a junction-to-ambient thermal resistance (θJA) of 37 °C/W (still air), per Table 4 of the datasheet. At full load (45 mA core current, 30 mA per active LVPECL output), junction temperature rise remains within safe limits (<85 °C ambient + 37 °C/W × 0.15 W ≈ 90.5 °C), well below the 150 °C absolute maximum rating.
SI5338N-B04890-GM Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- MultiSynth™
- Package/Case:
- 24-VFQFN Exposed Pad
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- PLL:
- -
- Main Purpose:
- -
- Input:
- -
- Output:
- -
- Number of Circuits:
- -
- Ratio - Input:Output:
- -
- Differential - Input:Output:
- -
- Frequency - Max:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 24-QFN (4x4)
SI5338N-B04890-GM FAQ
1.How can I place an order for SI5338N-B04890-GM through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5338N-B04890-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5338N-B04890-GM reliable?
The price and inventory of SI5338N-B04890-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338N-B04890-GM is usually 5 days.
3.What payment methods are accepted for SI5338N-B04890-GM?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338N-B04890-GM transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5338N-B04890-GM?
SI5338N-B04890-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5338N-B04890-GM order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5338N-B04890-GM?
For technical support, including SI5338N-B04890-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338N-B04890-GM requirements.
6.How does Aetrix verify that SI5338N-B04890-GM is sourced from the original manufacturer or authorized distributors?
All SI5338N-B04890-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338N-B04890-GM meets industry standards.
7.What is the process for return or replacement of SI5338N-B04890-GM?
All SI5338N-B04890-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338N-B04890-GM, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5338N-B04890-GM part is unused and in its original packaging.
Return procedure for SI5338N-B04890-GM:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SI5338N-B04890-GM Tags

-
LMK00334RTVRQ1
Texas Instruments
.jpg)
-
DSC557-0344FI0T
Microchip Technology

-
9FGV0241AKILFT
Renesas

-
9DBL0452CKILFT
Renesas
.jpg)
-
DSC557-0344FL1T
Microchip Technology
-
RC19008AGND#KB0
Renesas
-
RC19008AGND#BB0
Renesas

-
9DB403DGILFT
Renesas

-
9DB233AGILFT
Renesas

-
9DB803DGILFT
Renesas

-
9FGL0851DKILFT
Renesas
-
AB-557-03-HCHC-F-L-C-T
Abracon LLC
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

