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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338N-B04890-GMR

Name: SI5338N-B04890-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338N-B04890-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338N-B04890-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338N-B04890-GMR.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5338N-B04890-GMR from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation across –40 to +85 °C in a 4 × 4 mm 24-QFN package. It replaces up to four crystal oscillators in high-speed serial interface timing applications.

For engineers reviewing the SI5338N-B04890-GMR datasheet, SI5338N-B04890-GMR pinout, SI5338N-B04890-GMR application, or SI5338N-B04890-GMR equivalent, key selection considerations include its MultiSynth™-based any-frequency synthesis (0.16–710 MHz per output), independent output voltage support (1.5/1.8/2.5/3.3 V), spread-spectrum capability (0.5–5.0% down-spread), and I²C/SMBus programmability with ClockBuilder Pro software integration.

Technical Context

The SI5338N-B04890-GMR implements a two-stage PLL architecture: a high-stability reference PLL (Stage 1) locks to one of six input sources (crystal, CMOS, SSTL/HSTL, or differential), followed by four independent MultiSynth™ fractional-N synthesizers (Stage 2) generating each output. Each synthesizer supports integer or fractional mode with <1 ppb frequency resolution and programmable initial phase offset (±45 ns).

Its output stage provides per-driver configurability for signal format (LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL), termination voltage (VDDOx = 1.4–3.63 V), and optional spread-spectrum modulation (33–63 kHz rate, 0.5–5.0% deviation). Loss-of-lock and loss-of-signal alarms, plus independent frequency/phase increment/decrement control (20 ps step accuracy), enable dynamic system-level timing adaptation.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 3 SRNS and Gen 4 common clock jitter requirements
Output Frequency Range	0.16–710 MHz per channel; supports up to two >350 MHz outputs simultaneously (Fvco/4 & Fvco/6)
Input Reference Support	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz)
Output Driver Flexibility	Up to four differential outputs, eight single-ended, or mixed configuration; independent VDDO per driver (1.5/1.8/2.5/3.3 V)
Core Supply Voltage	1.8 V (±5%), 2.5 V (±10%), or 3.3 V (±10%); 45 mA typical core current at 100 MHz on all outputs
Operating Temperature	–40 to +85 °C; qualified for industrial and telecom line card environments
I²C Interface	SMBus-compatible; supports ClockBuilder Pro programming and real-time register access for dynamic reconfiguration

Pinout & Package

SI5338N-B04890-GMR is housed in a 4 × 4 mm, 24-lead QFN package with exposed thermal pad. Pin assignments are fixed per the Si5338 family: inputs (IN1–IN6), outputs (CLK0A/B through CLK3A/B), power (VDD, VDDO0–VDDO3), control (SCL, SDA, INTR), and reserved ground (RSVD_GND).

Pin/Terminal	Circuit Role	Design Meaning
IN1/IN2, IN5/IN6	Differential input pairs	Accept 5–710 MHz AC-coupled differential clocks; require external 100 Ω termination
IN3/IN4	Single-ended input pins	Support 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL with DC coupling
CLK0A/CLK0B – CLK3A/CLK3B	Differential output pairs	Four independent LVPECL/LVDS/HCSL/CML outputs; each with dedicated VDDO supply
VDDO0–VDDO3	Output buffer supplies	Enable per-output voltage setting (1.4–3.63 V) for level translation and interface compatibility
SCL/SDA	I²C serial interface	Allow full device configuration, status monitoring, and real-time frequency/phase adjustment
INTR	Interrupt output	Asserts on loss-of-lock or loss-of-signal events; open-drain, requires external pull-up

Key Features

Feature	Design Value
MultiSynth™ any-frequency synthesis	Generates four independent, zero-ppm-accurate output frequencies from a single reference-eliminates need for multiple crystals or oscillators
PCIe Gen 1–4 and SRNS compliance	Meets total jitter (33.6 ps pk-pk Gen 2), RMS jitter (0.11–0.45 ps RMS Gen 3/4), and deterministic jitter specs without external filtering
Independent output voltage per driver	Enables direct interfacing with mixed-voltage systems (e.g., 1.8 V FPGA core + 3.3 V PHY) without level shifters
Programmable spread spectrum	Reduces EMI peak emissions by up to 5% down-spread at 33–63 kHz-configurable per output without affecting others
Glitchless frequency adjustment	1 ppm step size with pin- or I²C-controlled increment/decrement enables real-time clock tuning during system operation
External feedback mode	Supports zero-delay clock distribution by feeding back a system clock to INx, synchronizing outputs to board-level timing

Applications

PCIe Gen 4 Switch Timing	Ethernet Switch/Routing
Use Scenario: High-density 32-lane PCIe Gen 4 switch ASIC requiring four synchronized, low-jitter clocks for SerDes lanes, management interfaces, and memory controllers. IC Role / Device Role / Timing Role: Quad clock generator providing independent 100 MHz (HCSL), 250 MHz (LVDS), 125 MHz (LVDS), and 156.25 MHz (LVPECL) outputs with sub-0.5 ps RMS jitter. Use Value: Meets PCIe Gen 4 common clock TJ spec (≤33.6 ps pk-pk) and eliminates inter-clock skew between lanes via precise phase alignment (<20 ps step resolution).	Use Scenario: 10 GbE/25 GbE Ethernet switch line card needing separate clocks for MAC, PHY, packet buffer, and CPU subsystems. IC Role / Device Role / Timing Role: Configurable clock source delivering 156.25 MHz (CMOS), 312.5 MHz (LVDS), 125 MHz (HCSL), and 25 MHz (LVPECL) with independent voltage domains. Use Value: Reduces BOM count by replacing four discrete oscillators; supports IEEE 802.3bj jitter compliance via MultiSynth™ fractional synthesis and low additive jitter (<0.7 ps RMS).
Broadcast Video Timing	FPGA-Based Processor Clocking
Use Scenario: SMPTE ST 2110 IP video router requiring genlock-capable, frame-synchronous clocks for video, audio, and ancillary data streams. IC Role / Device Role / Timing Role: Master timing IC generating 74.25 MHz (LVDS), 148.5 MHz (LVDS), 297 MHz (LVDS), and 27 MHz (CMOS) with programmable phase offsets for lip-sync alignment. Use Value: Enables sub-frame timing precision (±45 ns initial offset, <20 ps adjustment steps) and seamless switching between primary/backup reference inputs (IN1/IN2).	Use Scenario: Xilinx Versal or Intel Agilex FPGA platform requiring multiple domain-specific clocks (PL fabric, PS core, DDR4, transceivers). IC Role / Device Role / Timing Role: Flexible clock synthesizer supplying 300 MHz (LVDS), 100 MHz (HCSL), 200 MHz (LVDS), and 125 MHz (CMOS) with independent VDDO for mixed-voltage I/O banks. Use Value: Eliminates external clock buffers and level translators; simplifies PCB layout with single 4×4 mm QFN and supports dynamic reconfiguration via I²C during FPGA partial reconfiguration.

PCIe Gen 4 Switch Timing

Ethernet Switch/Routing

Use Scenario: High-density 32-lane PCIe Gen 4 switch ASIC requiring four synchronized, low-jitter clocks for SerDes lanes, management interfaces, and memory controllers.

IC Role / Device Role / Timing Role: Quad clock generator providing independent 100 MHz (HCSL), 250 MHz (LVDS), 125 MHz (LVDS), and 156.25 MHz (LVPECL) outputs with sub-0.5 ps RMS jitter.

Use Value: Meets PCIe Gen 4 common clock TJ spec (≤33.6 ps pk-pk) and eliminates inter-clock skew between lanes via precise phase alignment (<20 ps step resolution).

Use Scenario: 10 GbE/25 GbE Ethernet switch line card needing separate clocks for MAC, PHY, packet buffer, and CPU subsystems.

IC Role / Device Role / Timing Role: Configurable clock source delivering 156.25 MHz (CMOS), 312.5 MHz (LVDS), 125 MHz (HCSL), and 25 MHz (LVPECL) with independent voltage domains.

Use Value: Reduces BOM count by replacing four discrete oscillators; supports IEEE 802.3bj jitter compliance via MultiSynth™ fractional synthesis and low additive jitter (<0.7 ps RMS).

Broadcast Video Timing

FPGA-Based Processor Clocking

Use Scenario: SMPTE ST 2110 IP video router requiring genlock-capable, frame-synchronous clocks for video, audio, and ancillary data streams.

IC Role / Device Role / Timing Role: Master timing IC generating 74.25 MHz (LVDS), 148.5 MHz (LVDS), 297 MHz (LVDS), and 27 MHz (CMOS) with programmable phase offsets for lip-sync alignment.

Use Value: Enables sub-frame timing precision (±45 ns initial offset, <20 ps adjustment steps) and seamless switching between primary/backup reference inputs (IN1/IN2).

Use Scenario: Xilinx Versal or Intel Agilex FPGA platform requiring multiple domain-specific clocks (PL fabric, PS core, DDR4, transceivers).

IC Role / Device Role / Timing Role: Flexible clock synthesizer supplying 300 MHz (LVDS), 100 MHz (HCSL), 200 MHz (LVDS), and 125 MHz (CMOS) with independent VDDO for mixed-voltage I/O banks.

Use Value: Eliminates external clock buffers and level translators; simplifies PCB layout with single 4×4 mm QFN and supports dynamic reconfiguration via I²C during FPGA partial reconfiguration.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D08880-GM	Higher integration: 8 outputs, integrated LDOs, lower jitter (0.35 ps RMS), supports JESD204B deterministic latency	Targeted at JESD204B ADC/DAC timing and multi-ASIC synchronization where deterministic delay matters	Choose when >4 outputs or sub-0.4 ps jitter required; not drop-in due to different pinout and power architecture
ICS8430I-01T	Fixed-frequency, non-programmable; 4 LVDS outputs only; no I²C interface; higher jitter (1.2 ps RMS)	Cost-sensitive, static clock tree applications where frequency flexibility is unnecessary	Choose for simple, low-cost replacement of legacy oscillators where field reprogramming is not needed

Compared with SI5338N-B04890-GMR, Si5332A-D08880-GM offers superior jitter and scalability but requires board redesign, while ICS8430I-01T sacrifices programmability and performance for cost-making SI5338N-B04890-GMR optimal for field-upgradable, multi-standard timing in space-constrained industrial and telecom designs.

Availability

SI5338N-B04890-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, Ethernet switch/routing, and broadcast video timing requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.

Supply support for SI5338N-B04890-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and mobile markets.

The Si5338 product line delivers programmable, low-jitter clock generation for high-speed serial interfaces-including PCIe, Ethernet, and broadcast video-enabling flexible, future-proof timing architectures in compact form factors.

FAQ

What is the maximum output frequency supported by SI5338N-B04890-GMR?

The SI5338N-B04890-GMR supports up to 710 MHz on LVPECL/LVDS/CML outputs, 350 MHz on SSTL/HSTL, 250 MHz on HCSL, and 200 MHz on CMOS. However, only two unique frequencies above 350 MHz can be generated simultaneously-specifically Fvco/4 and Fvco/6-as defined by the internal VCO architecture. All other outputs must remain ≤350 MHz.

Does SI5338N-B04890-GMR support PCIe Gen 4 Common Clock compliance?

Yes, SI5338N-B04890-GMR meets PCIe Gen 4 Common Clock RMS jitter requirements (≤0.45 ps RMS, 10 kHz–50 MHz) when configured per Skyworks AN562 guidelines using HCSL outputs at 100 MHz. Its measured 0.15–0.45 ps RMS jitter range under specified test conditions validates compliance without external jitter cleaners.

Can SI5338N-B04890-GMR generate different output voltages on each channel?

Yes, SI5338N-B04890-GMR provides independent VDDO0–VDDO3 supplies, allowing each of its four output drivers to operate at 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This enables direct interface with mixed-voltage components-such as a 1.8 V FPGA core and 3.3 V Ethernet PHY-without external level shifters or voltage translators.

How is SI5338N-B04890-GMR programmed, and what tools are required?

SI5338N-B04890-GMR is programmed via its I²C/SMBus interface using Skyworks' ClockBuilder Pro software. The tool auto-generates configuration files, validates timing constraints, and exports register maps for integration into boot firmware. No external hardware programmer is needed-only a standard I²C host controller or USB-to-I²C adapter.

What is the thermal performance of SI5338N-B04890-GMR in continuous operation?

SI5338N-B04890-GMR has a junction-to-ambient thermal resistance (θJA) of 37 °C/W in still air. At typical operating conditions (100 MHz on all outputs, 3.3 V core), its 45 mA core current yields ~150 mW dissipation, resulting in a ~5.6 °C junction-to-ambient rise-well within its –40 to +85 °C ambient rating and compatible with standard 2-layer PCB layouts without forced airflow.

SI5338N-B04890-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338N-B04890-GMR FAQ

1.How can I place an order for SI5338N-B04890-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338N-B04890-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338N-B04890-GMR reliable?

The price and inventory of SI5338N-B04890-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338N-B04890-GMR is usually 5 days.

3.What payment methods are accepted for SI5338N-B04890-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338N-B04890-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338N-B04890-GMR?

SI5338N-B04890-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338N-B04890-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338N-B04890-GMR?

For technical support, including SI5338N-B04890-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338N-B04890-GMR requirements.

6.How does Aetrix verify that SI5338N-B04890-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338N-B04890-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338N-B04890-GMR meets industry standards.

7.What is the process for return or replacement of SI5338N-B04890-GMR?

All SI5338N-B04890-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338N-B04890-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338N-B04890-GMR part is unused and in its original packaging.

Return procedure for SI5338N-B04890-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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