Skyworks Solutions Inc. SI5338N-B04892-GMR
- Part No.:
- SI5338N-B04892-GMR
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Application Specific Clock/Timing
- Package:
- 24-VFQFN Exposed Pad
- Datasheet:
-
SI5338N-B04892-GMR.pdf
- Description:
- I2C CONTROL, 4-OUTPUT, ANY FREQU
- Quantity:
- Payment:

- Shipping:

Inventory:4,493
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SI5338N-B04892-GMR from Skyworks Solutions is an I²C-programmable quad clock generator IC with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 and SRNS compliance, and MultiSynth™ frequency synthesis supporting 0.16–710 MHz output ranges across LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats. It replaces up to four crystal oscillators in high-speed serial interface timing applications.
For engineers reviewing the SI5338N-B04892-GMR datasheet, SI5338N-B04892-GMR pinout, SI5338N-B04892-GMR application, or SI5338N-B04892-GMR equivalent, key selection criteria include its 24-QFN package, independent per-output voltage (1.5/1.8/2.5/3.3 V), programmable phase/frequency increment (±45 ns / <20 ps step), spread-spectrum capability (0.5–5.0% down-spread), and support for external crystal (8–30 MHz) or wide-band differential inputs (5–710 MHz).
Technical Context
The SI5338N-B04892-GMR implements a two-stage PLL architecture: a high-stability reference stage followed by four independent MultiSynth™ fractional-N synthesis blocks, each driving a configurable output buffer. Its input stage accepts eight distinct reference sources - including differential (IN1/IN2, IN5/IN6), single-ended CMOS (IN3/IN4), SSTL/HSTL, and external crystal - with automatic loss-of-signal detection.
Each of the four output drivers supports independent format selection (LVPECL, LVDS, HCSL, CMOS, SSTL, HSTL), independent supply voltage (VDDO0–VDDO3), and independent phase/frequency adjustment. The device operates across –40 to +85 °C with core supply options at 1.8 V, 2.5 V, or 3.3 V and delivers 45 mA typical core current at full 100 MHz output load.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Phase Jitter (RMS) | 0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 3/4 SRNS and GbE jitter requirements |
| Output Frequency Range | 0.16–710 MHz depending on format: LVPECL/LVDS up to 710 MHz, HCSL up to 250 MHz, CMOS up to 200 MHz |
| Input Reference Support | External crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz) |
| Output Driver Flexibility | Four differential outputs (CLK0A/B–CLK3A/B), eight single-ended outputs, or mixed configuration; each with independent VDDO (1.5/1.8/2.5/3.3 V) |
| Programmability | I²C/SMBus interface; ClockBuilder Pro software support; OTP NVM storage for factory programming |
| Supply & Thermal | Core supply: 1.8/2.5/3.3 V ±10%; θJA = 37 °C/W; operating ambient: –40 to +85 °C |
| Package | 24-pin QFN, 4 × 4 mm, 0.5 mm pitch, exposed thermal pad |
Pinout & Package
SI5338N-B04892-GMR is housed in a 24-lead, 4 × 4 mm QFN package with exposed thermal pad (pin 24). Pin assignments are fixed per the Si5338 family: dual differential inputs (IN1/IN2, IN5/IN6), dual single-ended inputs (IN3/IN4), four differential output pairs (CLK0A/B–CLK3A/B), four independent VDDO supplies (VDDO0–VDDO3), shared VDD core, SCL/SDA/I²C interface, INTR alarm output, and reserved ground.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN1, IN2, IN5, IN6 | Differential clock inputs | Accept AC-coupled LVPECL/LVDS/CML references up to 710 MHz; internal 100 Ω termination enabled |
| IN3, IN4 | Single-ended clock inputs | Support CMOS/SSTL/HSTL signals (5–350 MHz); 20 kΩ pull-up/pull-down configurable via register |
| CLK0A–CLK3B (x4 pairs) | Differential output drivers | Each pair supports LVPECL/LVDS/HCSL/CML; independently voltage- and format-configurable |
| VDDO0–VDDO3 | Output buffer supplies | Decoupled per-output-group supplies enabling mixed-voltage operation (1.5/1.8/2.5/3.3 V) |
| VDD | Core supply | Single 1.8/2.5/3.3 V supply powering PLL, synthesizers, and control logic |
| SCL, SDA | I²C interface | Standard SMBus-compatible 100/400 kHz interface; supports hot-plug and multi-drop configurations |
| INTR | Interrupt output | Open-drain status signal indicating loss-of-lock or loss-of-signal events |
Key Features
| Feature | Design Value |
|---|---|
| Independent per-output phase adjustment | ±45 ns range with <20 ps resolution enables precise inter-clock skew alignment in multi-lane SerDes systems |
| Glitchless frequency tuning | 1 ppm step size with pin-controlled increment/decrement allows real-time dynamic frequency adaptation without output interruption |
| PCIe Gen 4 Common Clock compliance | 0.15–0.45 ps RMS jitter (10 kHz–50 MHz) satisfies PCIe Base Spec 4.0 rev 0.5 timing budgets for host and endpoint clocks |
| Zero-ppm synthesis accuracy | MultiSynth™ fractional-N architecture eliminates long-term frequency drift versus crystal-based solutions |
| Configurable spread spectrum | 0.5–5.0% down-spread at 33–63 kHz modulation rate reduces EMI peak emissions in dense PCB layouts |
Applications
| PCIe Gen 4 Switch Timing | Ethernet Switch Clocking |
|---|---|
Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe Gen 4 switch ASICs in a data center fabric card. IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent, low-jitter, spread-spectrum-enabled clocks meeting PCIe Gen 4 Common Clock jitter spec (≤0.45 ps RMS). Use Value: Eliminates need for four discrete oscillators; reduces board area by >60% and enables per-port frequency margining via I²C. | Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10/25 GbE PHYs and MACs on a telecom line card. IC Role / Device Role / Timing Role: Any-frequency synthesizer producing exact IEEE 802.3-compliant rates with sub-ppm accuracy and <1 ps RMS jitter. Use Value: Supports mixed-speed Ethernet interfaces on one chip; avoids external jitter cleaners and simplifies BOM management. |
| Broadcast Video Sync Generator | FPGA-Based Video Processing |
Use Scenario: Deriving SMPTE ST 2082 (27 Gbps) and ST 2081 (12 Gbps) reference clocks from a common 27 MHz crystal in broadcast camera backends. IC Role / Device Role / Timing Role: High-precision frequency translator converting 27 MHz to 27 GHz-related rates (e.g., 594 MHz, 1.188 GHz) using integer-mode MultiSynth™. Use Value: Achieves <10 ps pk-pk period jitter required for uncompressed 4K/8K video transport; supports frame-accurate genlock via programmable phase offset. | Use Scenario: Supplying 300 MHz system clock, 150 MHz DDR4 memory clock, and 250 MHz transceiver reference to Xilinx Versal FPGA in AI inference accelerator. IC Role / Device Role / Timing Role: Configurable quad clock source with independent VDDO supplies enabling mixed-voltage domain timing (1.8 V I/O, 1.2 V core, 0.85 V transceiver). Use Value: Removes need for separate clock buffers and level translators; reduces power delivery complexity and improves timing closure. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad clock generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5332A-D08889-GM | Higher integration: includes integrated LDOs, enhanced PCIe Gen 5 jitter performance (0.12 ps RMS), 32-QFN package | Targeted for next-gen server and AI accelerators requiring Gen 5 compliance and simplified power design | Select when Gen 5 readiness, lower jitter, or integrated power is required; not drop-in due to different pinout and register map |
| ICS8430I-01T | Fixed-frequency, non-programmable quad LVDS output; no I²C interface; 0.9 ps RMS jitter; 32-TQFP package | Used in cost-sensitive, stable-frequency applications where reconfiguration is unnecessary | Select for production designs with unchanging clock trees and strict cost targets; requires external configuration resistors and lacks dynamic tuning |
Compared with Si5332A-D08889-GM and ICS8430I-01T, SI5338N-B04892-GMR offers optimal balance of field-programmability, PCIe Gen 4 compliance, and compact 24-QFN footprint-making it ideal for mid-life-cycle upgrades and multi-protocol systems where flexibility outweighs Gen 5 readiness or lowest-cost fixed-function alternatives.
Availability
SI5338N-B04892-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, Ethernet switch clocking, and broadcast video sync generation requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.
Supply support for SI5338N-B04892-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.
The Si5338 product line was designed to replace multiple discrete oscillators and clock buffers in high-speed digital systems, delivering any-frequency synthesis with ultra-low jitter and flexible output formatting for SerDes, processor, and FPGA clocking.
FAQ
What is the maximum output frequency supported by SI5338N-B04892-GMR in LVPECL mode?
The SI5338N-B04892-GMR supports up to 710 MHz in LVPECL output mode, as specified in Table 6 of the datasheet under "Output Clocks (Differential)" for LVPECL/LVDS/CML formats. This applies when using integer-mode MultiSynth™ synthesis and proper layout practices-including controlled impedance routing and adequate power decoupling-to maintain jitter performance below 1 ps RMS.
Does SI5338N-B04892-GMR support PCIe Gen 4 Separate Reference No Spread (SRNS) timing?
Yes, SI5338N-B04892-GMR is explicitly compliant with PCIe Gen 4 SRNS requirements, delivering ≤0.32 ps RMS jitter (10 kHz–50 MHz) when configured with PLL bandwidth of 2–4 MHz and CDR set to 10 MHz. This is verified in Table 12 of the datasheet and confirmed by Skyworks' PCIe Clock Jitter Tool validation reports.
Can SI5338N-B04892-GMR generate four different output frequencies simultaneously?
Yes, SI5338N-B04892-GMR can synthesize four independent output frequencies simultaneously-each with zero ppm error-using its four dedicated MultiSynth™ synthesis blocks. Frequencies may differ in format (e.g., CLK0A = LVDS @ 100 MHz, CLK1A = HCSL @ 156.25 MHz), voltage (VDDO0 = 1.8 V, VDDO1 = 2.5 V), and jitter profile, all programmed via I²C.
What crystal frequency range is compatible with SI5338N-B04892-GMR?
SI5338N-B04892-GMR supports external crystals from 8 to 30 MHz, segmented into four validated bands: 8–11 MHz, 11–19 MHz, 19–26 MHz, and 26–30 MHz. Each band has defined load capacitance (17–19 pF recommended), ESR limits (≤300 Ω), and drive level (≤100 µW) per Tables 8–11 in the datasheet.
Is SI5338N-B04892-GMR pin-compatible with other Si5338 variants like SI5338A or SI5338B?
Yes, all Si5338 variants-including SI5338N-B04892-GMR-share identical 24-QFN pinout, electrical interface, and register map. Differences lie only in factory-programmed configuration (e.g., default output frequencies, spread-spectrum settings, and I²C address), making them hardware-compatible replacements within the same package footprint.
SI5338N-B04892-GMR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- MultiSynth™
- Package/Case:
- 24-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- PLL:
- -
- Main Purpose:
- -
- Input:
- -
- Output:
- -
- Number of Circuits:
- -
- Ratio - Input:Output:
- -
- Differential - Input:Output:
- -
- Frequency - Max:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 24-QFN (4x4)
SI5338N-B04892-GMR FAQ
1.How can I place an order for SI5338N-B04892-GMR through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5338N-B04892-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5338N-B04892-GMR reliable?
The price and inventory of SI5338N-B04892-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338N-B04892-GMR is usually 5 days.
3.What payment methods are accepted for SI5338N-B04892-GMR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338N-B04892-GMR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5338N-B04892-GMR?
SI5338N-B04892-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5338N-B04892-GMR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5338N-B04892-GMR?
For technical support, including SI5338N-B04892-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338N-B04892-GMR requirements.
6.How does Aetrix verify that SI5338N-B04892-GMR is sourced from the original manufacturer or authorized distributors?
All SI5338N-B04892-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338N-B04892-GMR meets industry standards.
7.What is the process for return or replacement of SI5338N-B04892-GMR?
All SI5338N-B04892-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338N-B04892-GMR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5338N-B04892-GMR part is unused and in its original packaging.
Return procedure for SI5338N-B04892-GMR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SI5338N-B04892-GMR Tags

-
LMK00334RTVRQ1
Texas Instruments
.jpg)
-
DSC557-0344FI0T
Microchip Technology

-
9FGV0241AKILFT
Renesas

-
9DBL0452CKILFT
Renesas
.jpg)
-
DSC557-0344FL1T
Microchip Technology
-
RC19008AGND#KB0
Renesas
-
RC19008AGND#BB0
Renesas

-
9DB403DGILFT
Renesas

-
9DB233AGILFT
Renesas

-
9DB803DGILFT
Renesas

-
9FGL0851DKILFT
Renesas
-
AB-557-03-HCHC-F-L-C-T
Abracon LLC
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

