Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338N-B04992-GMR

Name: SI5338N-B04992-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338N-B04992-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: SI5338N-B04992-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338N-B04992-GMR.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:2,834

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

SI5338N-B04992-GMR from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation across –40 to +85 °C. It replaces up to four crystal oscillators in high-speed serial interface timing applications.

For engineers reviewing the SI5338N-B04992-GMR datasheet, SI5338N-B04992-GMR pinout, SI5338N-B04992-GMR application, or SI5338N-B04992-GMR equivalent, key selection criteria include output format flexibility (LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL), independent per-output voltage control (1.5–3.3 V), any-frequency synthesis capability (0.16–710 MHz), and PCIe Gen 4 jitter compliance (0.15–0.45 ps RMS).

Technical Context

The SI5338N-B04992-GMR implements a two-stage PLL architecture with a high-frequency VCO and patented MultiSynth™ fractional-N synthesis per output, enabling independent frequency generation with 1 ppb resolution and true zero-ppm accuracy. Input reference support includes external crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), and differential (5–710 MHz) sources.

Each of the four output drivers supports independent configuration for signal format, supply voltage (VDDOx = 1.5/1.8/2.5/3.3 V), spread-spectrum modulation (0.5–5.0% spread, 33–63 kHz rate), and fine-grained phase adjustment (<20 ps steps). Loss-of-lock and loss-of-signal alarms provide real-time status monitoring via the INTR pin.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 4 common clock jitter spec (≤0.45 ps RMS).
Output Frequency Range	0.16–710 MHz per channel; LVPECL/LVDS up to 710 MHz, HCSL up to 250 MHz, CMOS up to 200 MHz.
Input Reference Support	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz).
Supply Voltages	Core: 1.8/2.5/3.3 V ±10%; Output buffers: independently configurable 1.5/1.8/2.5/3.3 V.
Operating Temperature	–40 to +85 °C; qualified for industrial and telecom line card environments.
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch; RoHS-compliant, GMR suffix indicates green packaging.
Power Consumption	45 mA typical core current at 100 MHz on all outputs and 25 MHz reference clock.

Pinout & Package

SI5338N-B04992-GMR is housed in a 24-lead QFN package (4 mm × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin assignments are fixed per the Si5338 family and validated for this variant.

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2, IN5, IN6	Differential input pairs	Accept AC-coupled differential clocks up to 710 MHz; require external 100 Ω termination.
IN3, IN4	Single-ended input pins	Support CMOS/SSTL/HSTL inputs (5–350 MHz); VIH = 0.7×VDD, VIL = 0.3×VDD.
CLK0A/CLK0B to CLK3A/CLK3B	Differential output pairs	Four independent differential output channels; each configurable for LVPECL/LVDS/HCSL/CML.
VDDO0–VDDO3	Output buffer supplies	Independent 1.5/1.8/2.5/3.3 V supplies per output bank; enable mixed-voltage system interfacing.
SCL, SDA	I²C interface	SMBus-compatible 2-wire serial interface (up to 400 kHz) for configuration and status readback.
INTR	Interrupt output	Open-drain alarm pin asserting on loss-of-lock or loss-of-signal events.
VDD	Core supply	Single 1.8/2.5/3.3 V core supply; PSRR optimized for noise immunity.
GND, RSVD_GND	Ground terminals	Multiple dedicated ground pins including reserved ground for noise isolation and thermal management.

Key Features

Feature	Design Value
MultiSynth™ synthesis per output	Enables independent, any-frequency generation (0.16–710 MHz) with 0 ppm precision and 1 ppb resolution.
PCIe Gen 1–4 compliance	Meets Common Clock and Gen 3 SRNS jitter specs; validated using Skyworks PCIe Clock Jitter Tool.
Flexible output formatting	Each output supports LVPECL, LVDS, HCSL, CML, CMOS, SSTL, or HSTL - selectable per channel.
Independent phase/frequency tuning	Glitchless 1 ppm frequency step and <20 ps phase step adjustments via pin control or I²C.
Spread-spectrum capability	Configurable SSC on any output: 0.5–5.0% spread, 33–63 kHz modulation rate, programmable center/down-spread.
Zero-delay mode support	External feedback path enables deterministic latency alignment between input and output clocks.

Applications

PCIe Gen 4 Switch Timing	Ethernet Switch/Routing
Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe Gen 4 switch ICs in a data center fabric. IC Role / Device Role / Timing Role: Quad-output clock generator delivering four low-jitter, independently configured clocks meeting PCIe Gen 4 Common Clock jitter limits (≤0.45 ps RMS). Use Value: Eliminates need for four discrete oscillators; reduces board area by >60% and simplifies layout with single-device timing solution.	Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10 GbE PHYs and packet processors in enterprise switches. IC Role / Device Role / Timing Role: Configurable clock synthesizer supporting mixed-format outputs (LVDS for PHYs, CMOS for controllers) with independent voltage rails. Use Value: Enables single-chip timing for multi-rate Ethernet interfaces while maintaining sub-1 ps RMS jitter across all outputs.
Broadcast Video Timing	FPGA Processor Clocking
Use Scenario: Delivering SMPTE ST 2082 (27 Gbps) pixel clock and ancillary timing signals (e.g., 74.25 MHz, 148.5 MHz) in 4K/8K video processing systems. IC Role / Device Role / Timing Role: High-precision frequency translator generating exact broadcast-standard frequencies from a single crystal reference. Use Value: Achieves true zero-ppm accuracy on all outputs, eliminating frame sync errors and ensuring compliance with SMPTE jitter masks.	Use Scenario: Supplying core, memory, and I/O clocks to Xilinx Versal or Intel Agilex FPGAs in adaptive compute platforms. IC Role / Device Role / Timing Role: Programmable quad clock source with independent phase alignment and spread-spectrum control per domain. Use Value: Reduces EMI through per-output SSC tuning and enables precise inter-clock skew control (<100 ps) for high-speed SerDes links.

PCIe Gen 4 Switch Timing

Ethernet Switch/Routing

Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe Gen 4 switch ICs in a data center fabric.

IC Role / Device Role / Timing Role: Quad-output clock generator delivering four low-jitter, independently configured clocks meeting PCIe Gen 4 Common Clock jitter limits (≤0.45 ps RMS).

Use Value: Eliminates need for four discrete oscillators; reduces board area by >60% and simplifies layout with single-device timing solution.

Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10 GbE PHYs and packet processors in enterprise switches.

IC Role / Device Role / Timing Role: Configurable clock synthesizer supporting mixed-format outputs (LVDS for PHYs, CMOS for controllers) with independent voltage rails.

Use Value: Enables single-chip timing for multi-rate Ethernet interfaces while maintaining sub-1 ps RMS jitter across all outputs.

Broadcast Video Timing

FPGA Processor Clocking

Use Scenario: Delivering SMPTE ST 2082 (27 Gbps) pixel clock and ancillary timing signals (e.g., 74.25 MHz, 148.5 MHz) in 4K/8K video processing systems.

IC Role / Device Role / Timing Role: High-precision frequency translator generating exact broadcast-standard frequencies from a single crystal reference.

Use Value: Achieves true zero-ppm accuracy on all outputs, eliminating frame sync errors and ensuring compliance with SMPTE jitter masks.

Use Scenario: Supplying core, memory, and I/O clocks to Xilinx Versal or Intel Agilex FPGAs in adaptive compute platforms.

IC Role / Device Role / Timing Role: Programmable quad clock source with independent phase alignment and spread-spectrum control per domain.

Use Value: Reduces EMI through per-output SSC tuning and enables precise inter-clock skew control (<100 ps) for high-speed SerDes links.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5338A-B04992-GM	Same silicon, non-green (halogen-containing) packaging; identical electrical specs and pinout.	No difference in performance or use case; differs only in RoHS/halogen compliance level.	Select SI5338N-B04992-GMR for RoHS-compliant, halogen-free production; choose Si5338A-B04992-GM only if legacy compliance allows.
LMK04832ISQE/NOPB	Two PLLs (not four independent synthesis paths); higher power (75 mA typ); larger 48-QFN package.	Requires external fanout buffers for quad-output use; less flexible per-output format/voltage control.	Choose LMK04832ISQE/NOPB only when dual-loop jitter cleaning is required over independent synthesis; not drop-in compatible.

Compared with Si5338A-B04992-GM, SI5338N-B04992-GMR offers identical timing performance with halogen-free packaging; compared with LMK04832ISQE/NOPB, it delivers true per-output synthesis in half the footprint and 40% lower core current, but lacks dual-loop jitter attenuation.

Availability

SI5338N-B04992-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, Ethernet switching infrastructure, and broadcast video equipment requiring stable component supply, long-term lifecycle support, and RoHS-compliant packaging.

Supply support for SI5338N-B04992-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and mobile markets.

The Si5338 product line was designed for high-density, multi-protocol timing consolidation in networking, computing, and broadcast systems-enabling replacement of multiple oscillators with a single programmable device.

FAQ

What is the maximum differential input frequency supported by SI5338N-B04992-GMR?

The SI5338N-B04992-GMR supports differential input frequencies up to 710 MHz on pins IN1/IN2 and IN5/IN6. This capability enables direct interfacing with high-speed SerDes reference clocks and aligns with PCIe Gen 4 and 25G Ethernet timing requirements. The device maintains low additive jitter (<0.225 ps RMS wideband) even at these frequencies in buffer mode.

Does SI5338N-B04992-GMR support PCIe Gen 4 Separate Reference No Spread (SRNS) mode?

Yes, SI5338N-B04992-GMR is compliant with PCIe Gen 4 SRNS specifications, achieving ≤0.32 ps RMS jitter under defined test conditions (PLL BW 2–4 MHz, CDR = 10 MHz). This is verified per PCI-SIG Base Specification 4.0 rev. 0.5 and confirmed using the Skyworks PCIe Clock Jitter Tool.

Can SI5338N-B04992-GMR generate four different output frequencies simultaneously?

Yes, SI5338N-B04992-GMR uses independent MultiSynth™ engines per output to synthesize four distinct frequencies simultaneously - e.g., 100 MHz (PCIe), 125 MHz (GbE), 156.25 MHz (10GbE), and 200 MHz (FPGA I/O) - all with 0 ppm accuracy and sub-ps jitter. Each output is fully independent in frequency, format, and voltage.

What output voltage levels does SI5338N-B04992-GMR support per channel?

SI5338N-B04992-GMR supports independent output buffer supply voltages of 1.5 V, 1.8 V, 2.5 V, or 3.3 V per VDDOx pin (VDDO0–VDDO3). This allows direct interfacing with mixed-voltage SoCs, FPGAs, and PHYs without level-shifting components - for example, driving 1.8 V LVDS SerDes and 3.3 V CMOS controllers from one device.

Is ClockBuilder Pro software required to configure SI5338N-B04992-GMR?

No, ClockBuilder Pro is optional but strongly recommended for SI5338N-B04992-GMR configuration. The device can be programmed via standard I²C commands, but ClockBuilder Pro provides GUI-based frequency planning, jitter optimization, register file generation, and validation against PCIe/SONET/SDI standards - significantly reducing bring-up time and configuration risk.

SI5338N-B04992-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338N-B04992-GMR FAQ

1.How can I place an order for SI5338N-B04992-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338N-B04992-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338N-B04992-GMR reliable?

The price and inventory of SI5338N-B04992-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338N-B04992-GMR is usually 5 days.

3.What payment methods are accepted for SI5338N-B04992-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338N-B04992-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338N-B04992-GMR?

SI5338N-B04992-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338N-B04992-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338N-B04992-GMR?

For technical support, including SI5338N-B04992-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338N-B04992-GMR requirements.

6.How does Aetrix verify that SI5338N-B04992-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338N-B04992-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338N-B04992-GMR meets industry standards.

7.What is the process for return or replacement of SI5338N-B04992-GMR?

All SI5338N-B04992-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338N-B04992-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338N-B04992-GMR part is unused and in its original packaging.

Return procedure for SI5338N-B04992-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-09 Counterfeit Electronic Components: How to Detect, Authenticate, and Test Suspect Parts

Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…