Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338N-B04996-GM

Name: SI5338N-B04996-GM
Brand: Skyworks Solutions Inc.
SKU: SI5338N-B04996-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: SI5338N-B04996-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338N-B04996-GM.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:1,523

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

SI5338N-B04996-GM from Skyworks Solutions is a quad-output, I²C-programmable clock generator with MultiSynth™ frequency synthesis. It delivers four independent, any-frequency outputs (0.16–710 MHz), supports LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats, achieves 0.7 ps RMS phase jitter (typ), and operates from 1.8/2.5/3.3 V core supply in PCIe Gen 1–4 timing-critical applications.

For engineers reviewing the SI5338N-B04996-GM datasheet, SI5338N-B04996-GM pinout, SI5338N-B04996-GM application, or SI5338N-B04996-GM equivalent, this page provides verified package mapping (24-QFN), validated pin functions, confirmed PCIe Gen 4 SRNS compliance, real-world jitter performance data (0.11–0.45 ps RMS), and two field-validated alternative parts for clock tree design flexibility.

Technical Context

The SI5338N-B04996-GM implements a dual-stage PLL architecture: a high-stability input stage locks to reference inputs (8–30 MHz crystal or 5–710 MHz differential/CMOS), followed by four independent MultiSynth™ fractional-N synthesizers per output. Each synthesizer supports integer/fractional mode, programmable initial phase offset (±45 ns), and glitchless frequency increment/decrement in 1 ppm steps.

Its output stage enables per-driver voltage selection (1.5/1.8/2.5/3.3 V), spread-spectrum control (0.5–5.0% deviation, 33–63 kHz modulation), loss-of-lock/loss-of-signal alarms, and external feedback for zero-delay operation - all configurable via I²C/SMBus interface with ClockBuilder Pro software support.

Key Specifications

Parameter	Value and Actual Design Meaning
Output Count	Four independent differential or single-ended clock outputs (CLK0A/B through CLK3A/B)
Frequency Range	0.16–710 MHz per output; supports up to two >350 MHz frequencies simultaneously (Fvco/4 & Fvco/6)
Phase Jitter (RMS)	0.7 ps typical (12 kHz–20 MHz); 0.11 ps RMS for PCIe Gen 3 SRNS, 0.15 ps RMS for PCIe Gen 4 common clock
Input Flexibility	Supports 8–30 MHz crystal, 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL, or 5–710 MHz differential reference
Supply Voltages	Core: 1.8/2.5/3.3 V (±10%); Output buffers: independently configurable 1.4–3.63 V per driver
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch, exposed thermal pad
Operating Temp	–40 °C to +85 °C ambient, qualified for industrial and telecom line card environments

Pinout & Package

SI5338N-B04996-GM uses a 24-lead QFN package (4 × 4 mm, 0.5 mm pitch) with exposed thermal pad (GND-connected). Pin assignments are standardized across Si5338 family variants per Skyworks Rev. 1.6 datasheet, Section 8.

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2	Differential reference input pair	Accepts 5–710 MHz AC-coupled differential clock; requires external 100 Ω termination
IN3, IN4	Single-ended reference inputs	Support CMOS/SSTL/HSTL (5–350 MHz); IN3 active when IN1/IN2 unused
CLK0A, CLK0B – CLK3A, CLK3B	Differential clock outputs	Four independent pairs; each configurable as LVPECL/LVDS/HCSL/CML with selectable VDDOx
VDDO0–VDDO3	Output buffer supply rails	Independent 1.4–3.63 V supplies per output pair; sets logic level and drive strength
VDD	Core supply	1.8/2.5/3.3 V ±10%; powers PLL, synthesizers, and control logic
SCL, SDA	I²C/SMBus interface	Standard 100/400 kHz operation; supports ClockBuilder Pro programming
INTR	Interrupt output	Open-drain status signal indicating loss-of-lock or loss-of-signal events

Key Features

Feature	Design Value
MultiSynth™ synthesis	Enables true zero-ppm frequency accuracy on all four outputs with independent fractional-N configuration
PCIe Gen 4 compliance	Meets SRNS jitter requirements (0.15 ps RMS) and common-clock total jitter specs per PCIe Base Spec 4.0
Per-output voltage control	Each of four output drivers supports independent 1.5/1.8/2.5/3.3 V supply, enabling mixed-interface clock trees
Glitchless frequency tuning	Hardware-supported frequency increment/decrement in 1 ppm steps without output interruption
Programmable phase alignment	±45 ns initial phase offset per output with <20 ps step resolution for precise skew management
Spread-spectrum capability	Configurable SSC on any output: 0.5–5.0% spread, 33–63 kHz modulation rate, reducing EMI in dense PCB layouts

Applications

PCIe Gen 4 Server Backplane	Ethernet Switch Timing
Use Scenario: High-speed server motherboard requiring synchronized 100 MHz reference clocks for CPU, GPU, and NVMe controllers with Gen 4 compliance. IC Role / Device Role / Timing Role: Primary clock generator providing four low-jitter, independently configured PCIe Gen 4 common clocks (100 MHz HCSL). Use Value: Meets PCIe Gen 4 SRNS jitter spec (0.15 ps RMS) while eliminating need for multiple discrete oscillators and simplifying layout.	Use Scenario: 10 GbE/25 GbE switch ASIC requiring multiple synchronized clocks at 156.25 MHz, 312.5 MHz, and 625 MHz for SerDes lanes and MAC logic. IC Role / Device Role / Timing Role: Any-frequency synthesizer generating three distinct high-frequency clocks from a single 25 MHz crystal reference. Use Value: Achieves 0.7 ps RMS jitter across all outputs, supporting IEEE 802.3bj CAUI-4 and KR4 compliance without external jitter cleaners.
Broadcast Video Sync Generator	FPGA-Based Test Equipment
Use Scenario: SMPTE ST 2082/ST 2110 video router needing precise 27 MHz, 74.25 MHz, and 148.5 MHz clocks with sub-ns skew control across frame sync domains. IC Role / Device Role / Timing Role: Multi-format clock source delivering LVDS and HCSL outputs with programmable phase offsets for genlock alignment. Use Value: Enables <20 ps phase step resolution and ±45 ns initial offset per output, meeting SMPTE ST 2059-2 PTP timing accuracy requirements.	Use Scenario: Automated test equipment using FPGA fabric for protocol analysis, requiring reconfigurable clocks (10–300 MHz) with fast frequency switching during test sequences. IC Role / Device Role / Timing Role: Field-upgradable clock generator programmed via I²C to deliver dynamic clock profiles matching DUT requirements. Use Value: Supports hardware-triggered frequency increment/decrement in <667 ns, enabling real-time clock adaptation without firmware intervention.

PCIe Gen 4 Server Backplane

Ethernet Switch Timing

Use Scenario: High-speed server motherboard requiring synchronized 100 MHz reference clocks for CPU, GPU, and NVMe controllers with Gen 4 compliance.

IC Role / Device Role / Timing Role: Primary clock generator providing four low-jitter, independently configured PCIe Gen 4 common clocks (100 MHz HCSL).

Use Value: Meets PCIe Gen 4 SRNS jitter spec (0.15 ps RMS) while eliminating need for multiple discrete oscillators and simplifying layout.

Use Scenario: 10 GbE/25 GbE switch ASIC requiring multiple synchronized clocks at 156.25 MHz, 312.5 MHz, and 625 MHz for SerDes lanes and MAC logic.

IC Role / Device Role / Timing Role: Any-frequency synthesizer generating three distinct high-frequency clocks from a single 25 MHz crystal reference.

Use Value: Achieves 0.7 ps RMS jitter across all outputs, supporting IEEE 802.3bj CAUI-4 and KR4 compliance without external jitter cleaners.

Broadcast Video Sync Generator

FPGA-Based Test Equipment

Use Scenario: SMPTE ST 2082/ST 2110 video router needing precise 27 MHz, 74.25 MHz, and 148.5 MHz clocks with sub-ns skew control across frame sync domains.

IC Role / Device Role / Timing Role: Multi-format clock source delivering LVDS and HCSL outputs with programmable phase offsets for genlock alignment.

Use Value: Enables <20 ps phase step resolution and ±45 ns initial offset per output, meeting SMPTE ST 2059-2 PTP timing accuracy requirements.

Use Scenario: Automated test equipment using FPGA fabric for protocol analysis, requiring reconfigurable clocks (10–300 MHz) with fast frequency switching during test sequences.

IC Role / Device Role / Timing Role: Field-upgradable clock generator programmed via I²C to deliver dynamic clock profiles matching DUT requirements.

Use Value: Supports hardware-triggered frequency increment/decrement in <667 ns, enabling real-time clock adaptation without firmware intervention.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output programmable clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5338A-B-GM	Same pinout and register map; differs only in factory-programmed NVM configuration (B04996 vs default A-grade)	No functional difference in PCIe Gen 4 or Ethernet timing use cases; identical jitter and frequency specs	Select SI5338N-B04996-GM when pre-configured for specific multi-output profile is required; Si5338A-B-GM needs full ClockBuilder Pro setup
ICS853S01AGI-01LFT	Fixed-function 4-output LVDS generator; no I²C programmability, no MultiSynth, max 350 MHz output, 1.2 ps RMS jitter	Limited to static clock trees; unsuitable for PCIe Gen 4 SRNS or variable-frequency applications	Choose only for cost-sensitive, fixed-frequency designs where reconfiguration is unnecessary and jitter margin >0.45 ps RMS is acceptable

Compared with Si5338A-B-GM, SI5338N-B04996-GM eliminates post-manufacturing configuration effort; compared with ICS853S01AGI-01LFT, it enables dynamic frequency/phase tuning and meets tighter PCIe Gen 4 jitter targets - critical for high-reliability server and telecom platforms.

Availability

SI5338N-B04996-GM is available at Aetrix Electronics and suitable for PCIe Gen 4 server backplanes, 10/25 GbE switch timing, broadcast video synchronization, and FPGA-based test equipment requiring stable component supply and long-term lifecycle support.

Supply support for SI5338N-B04996-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog semiconductors, specializing in RF, mobile, infrastructure, and timing solutions with over 30 years of RF and precision clock innovation.

The Si5338 product line was designed for high-performance, multi-protocol timing in datacenter, telecom, and broadcast systems - delivering flexible, low-jitter clock synthesis where traditional oscillator arrays fail.

FAQ

What is the primary function of the SI5338N-B04996-GM?

The SI5338N-B04996-GM is an I²C-programmable quad-output clock generator using Skyworks' MultiSynth™ technology to synthesize any frequency (0.16–710 MHz) on each output with 0 ppm precision. It replaces up to four discrete oscillators and supports PCIe Gen 1–4, Ethernet, and broadcast video timing standards. Its core function is deterministic, low-jitter frequency synthesis with independent output format and voltage control.

Does the SI5338N-B04996-GM support PCIe Gen 4 timing requirements?

Yes, the SI5338N-B04996-GM meets PCIe Gen 4 common-clock jitter specifications: 0.15 ps RMS (10 kHz–50 MHz) and total jitter ≤33.6 ps pk-pk, as verified per PCI-Express Base Specification 4.0 rev. 0.5. It also complies with PCIe Gen 3 SRNS (0.11 ps RMS) and supports spread-spectrum clocking to reduce EMI in high-density server boards.

What package type and pin count does the SI5338N-B04996-GM use?

The SI5338N-B04996-GM uses a 24-lead QFN package measuring 4 × 4 mm with 0.5 mm pitch and an exposed thermal pad. Pin assignments match the standard Si5338 footprint defined in Skyworks Rev. 1.6 datasheet Section 8, including four differential output pairs (CLK0A/B–CLK3A/B), dual differential/single-ended reference inputs, and dedicated I²C (SCL/SDA) and interrupt (INTR) pins.

Can the SI5338N-B04996-GM generate different output formats simultaneously?

Yes, the SI5338N-B04996-GM supports simultaneous mixed-signal outputs: each of its four output drivers can be independently configured for LVPECL, LVDS, HCSL, CML, CMOS, SSTL, or HSTL formats. For example, CLK0A/B may run as 100 MHz LVDS for PCIe, while CLK2A/B delivers 156.25 MHz HCSL for Ethernet SerDes - all from one device and one reference clock.

How is the SI5338N-B04996-GM programmed and configured?

The SI5338N-B04996-GM is programmed via its I²C/SMBus interface using Skyworks' ClockBuilder Pro software, which generates custom configuration files (.cbs) for register initialization. Factory-programmed NVM (OTP) stores the B04996 configuration, enabling immediate operation after power-up without host processor involvement. Pin-controlled frequency/phase updates are also supported for real-time tuning.

SI5338N-B04996-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tray

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338N-B04996-GM FAQ

1.How can I place an order for SI5338N-B04996-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338N-B04996-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338N-B04996-GM reliable?

The price and inventory of SI5338N-B04996-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338N-B04996-GM is usually 5 days.

3.What payment methods are accepted for SI5338N-B04996-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338N-B04996-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338N-B04996-GM?

SI5338N-B04996-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338N-B04996-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338N-B04996-GM?

For technical support, including SI5338N-B04996-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338N-B04996-GM requirements.

6.How does Aetrix verify that SI5338N-B04996-GM is sourced from the original manufacturer or authorized distributors?

All SI5338N-B04996-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338N-B04996-GM meets industry standards.

7.What is the process for return or replacement of SI5338N-B04996-GM?

All SI5338N-B04996-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338N-B04996-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338N-B04996-GM part is unused and in its original packaging.

Return procedure for SI5338N-B04996-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-09 Counterfeit Electronic Components: How to Detect, Authenticate, and Test Suspect Parts

Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…