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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338N-B05007-GM

Name: SI5338N-B05007-GM
Brand: Skyworks Solutions Inc.
SKU: SI5338N-B05007-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338N-B05007-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338N-B05007-GM.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

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Product details

Overview

SI5338N-B05007-GM from Skyworks Solutions is an I²C-programmable quad clock generator with four independent differential output drivers, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and support for LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL output formats across 0.16–710 MHz. It replaces up to four crystal oscillators in Ethernet switch/router and FPGA clocking systems.

For engineers reviewing the SI5338N-B05007-GM datasheet, SI5338N-B05007-GM pinout, SI5338N-B05007-GM application, or SI5338N-B05007-GM equivalent, key selection criteria include PCIe Gen 4 jitter compliance (0.15–0.45 ps RMS), independent per-output voltage control (1.5/1.8/2.5/3.3 V), MultiSynth™ fractional synthesis resolution (1 ppb), spread-spectrum capability (0.5–5.0% down-spread), and 24-QFN package compatibility with 4×4 mm PCB footprint constraints.

Technical Context

The SI5338N-B05007-GM implements a two-stage PLL architecture: a high-stability reference stage (with crystal or external clock input) followed by four independent MultiSynth™ synthesis blocks, each feeding a configurable output driver. Its fractional-N synthesis enables any-frequency generation without external loop filters.

Each of the four output drivers supports independent format selection (LVPECL, LVDS, HCSL, CMOS, SSTL, HSTL), independent supply voltage (VDDO0–VDDO3), programmable phase offset (±45 ns, <20 ps step), and glitchless frequency increment/decrement (1 ppm steps). Input flexibility includes 8–30 MHz crystal, 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL, or 5–710 MHz differential references.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 4 common clock jitter spec (0.15–0.45 ps RMS).
Output Frequency Range	0.16–710 MHz per channel; supports up to two outputs >350 MHz simultaneously (Fvco/4 & Fvco/6).
Synthesis Resolution	1 ppb; enables true zero-ppm accuracy on all four outputs via fractional-N MultiSynth™.
Input Reference Options	8–30 MHz crystal, 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL, or 5–710 MHz differential inputs.
Output Driver Flexibility	Four differential outputs (CLK0A/B–CLK3A/B); supports LVPECL, LVDS, HCSL, CMOS, SSTL, HSTL formats.
Supply Voltages	Core: 1.8/2.5/3.3 V; Output buffers: independently configurable 1.5/1.8/2.5/3.3 V per driver.
Spread Spectrum	Configurable per output: 0.5–5.0% down-spread, 33–63 kHz modulation rate.

Pinout & Package

SI5338N-B05007-GM uses a 24-pin QFN package (4 × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin assignments are standardized across Si5338 family variants per Skyworks Rev. 1.6 datasheet (Page 33, Pin Descriptions; Page 37, Device Pinout by Part Number).

Pin/Terminal	Circuit Role	Design Meaning
CLK0A / CLK0B CLK1A / CLK1B CLK2A / CLK2B CLK3A / CLK3B	Differential clock outputs (4 pairs)	Independent, fully configurable outputs supporting LVPECL/LVDS/HCSL/CML/SSTL/HSTL; each pair shares dedicated VDDOx supply rail.
VDDO0–VDDO3	Output buffer supply rails	Enable per-output voltage setting (1.5/1.8/2.5/3.3 V); decoupling required per rail for jitter performance.
IN1/IN2, IN5/IN6	Differential reference inputs	Accept 5–710 MHz AC-coupled differential clocks; require external 100 Ω termination.
IN3/IN4	Single-ended reference inputs	Accept 5–200 MHz CMOS-level clocks; support DC-coupled operation with internal biasing.
SCL / SDA	I²C configuration interface	Standard SMBus-compatible serial bus (up to 400 kHz); used with ClockBuilder Pro for register programming.
INTR	Interrupt output	Open-drain status signal indicating loss-of-lock or loss-of-signal events; requires external pull-up.
VDD	Core supply	1.8/2.5/3.3 V core power; PSRR optimized for clean timing operation under noisy system conditions.
GND / RSVD_GND	Ground connections	Multiple GND pins and reserved ground pad ensure low-impedance return path and thermal dissipation.

Key Features

Feature	Design Value
MultiSynth™ fractional-N synthesis	Enables any-frequency output generation (0.16–710 MHz) with 1 ppb resolution and zero-ppm accuracy-eliminates need for multiple crystals.
PCIe Gen 4 Common Clock compliance	0.15–0.45 ps RMS jitter at 100 MHz HCSL output satisfies PCI Express Base Spec 4.0 rev. 0.5 requirements.
Independent per-output voltage control	Four VDDOx rails allow mixed-voltage system interfacing (e.g., 1.8 V FPGA + 3.3 V PHY) without level shifters.
Glitchless frequency adjustment	1 ppm step size with pin-controlled increment/decrement enables real-time dynamic frequency tuning without output interruption.
Programmable spread spectrum	Per-output SSC (0.5–5.0% down-spread, 33–63 kHz) reduces EMI peak emissions in dense PCB layouts.

Applications

Ethernet Switch/Routing Timing	PCIe Gen 1–4 Clock Distribution
Use Scenario: High-port-count 10 GbE/25 GbE switches requiring synchronous, low-jitter clocks for SerDes lanes and packet processing logic. IC Role / Device Role / Timing Role: Quad clock generator providing four independent, jitter-clean clocks: one for MAC/PHY interface, one for CPU/FPGA fabric, one for management controller, and one for auxiliary peripherals. Use Value: 0.7 ps RMS phase jitter ensures compliance with IEEE 802.3bj CAUI-4 and 10GBASE-KR jitter masks; eliminates need for discrete jitter cleaners.	Use Scenario: Server motherboard with dual-CPU, multi-slot PCIe Gen 4 expansion, requiring common clock topology with strict jitter limits. IC Role / Device Role / Timing Role: Primary clock source delivering synchronized 100 MHz HCSL clocks to CPU socket, PCH, and PCIe slots while meeting PCIe Gen 4 SRNS (0.11–0.32 ps RMS) and common clock (0.15–0.45 ps RMS) specs. Use Value: Single-device replacement for four discrete oscillators reduces BOM count, layout area, and power consumption versus legacy solutions.
Broadcast Video/Audio Synchronization	FPGA & ASIC Clock Management
Use Scenario: SMPTE ST 2082-1 (12G-SDI) video transport equipment requiring precise genlock and frame-rate conversion. IC Role / Device Role / Timing Role: Multi-format clock synthesizer generating 74.25 MHz (12G-SDI), 27 MHz (SDI), 48 kHz audio sample clock, and 10 MHz reference from single crystal input. Use Value: Independent phase adjustment (<20 ps step) enables sub-pixel timing alignment across video pipelines; zero-ppm synthesis avoids long-term drift in broadcast master clocks.	Use Scenario: High-end adaptive computing platform using Xilinx Versal or Intel Agilex FPGAs with heterogeneous clock domains (PL, PS, transceivers, memory interfaces). IC Role / Device Role / Timing Role: Centralized clock hub supplying LVDS clocks to PL fabric, HCSL to GTY transceivers, SSTL to DDR4 controllers, and CMOS to microcontroller subsystems. Use Value: Per-output voltage and format configurability eliminates external level translators; I²C programmability enables runtime reconfiguration during partial reconfiguration sequences.

Ethernet Switch/Routing Timing

PCIe Gen 1–4 Clock Distribution

Use Scenario: High-port-count 10 GbE/25 GbE switches requiring synchronous, low-jitter clocks for SerDes lanes and packet processing logic.

IC Role / Device Role / Timing Role: Quad clock generator providing four independent, jitter-clean clocks: one for MAC/PHY interface, one for CPU/FPGA fabric, one for management controller, and one for auxiliary peripherals.

Use Value: 0.7 ps RMS phase jitter ensures compliance with IEEE 802.3bj CAUI-4 and 10GBASE-KR jitter masks; eliminates need for discrete jitter cleaners.

Use Scenario: Server motherboard with dual-CPU, multi-slot PCIe Gen 4 expansion, requiring common clock topology with strict jitter limits.

IC Role / Device Role / Timing Role: Primary clock source delivering synchronized 100 MHz HCSL clocks to CPU socket, PCH, and PCIe slots while meeting PCIe Gen 4 SRNS (0.11–0.32 ps RMS) and common clock (0.15–0.45 ps RMS) specs.

Use Value: Single-device replacement for four discrete oscillators reduces BOM count, layout area, and power consumption versus legacy solutions.

Broadcast Video/Audio Synchronization

FPGA & ASIC Clock Management

Use Scenario: SMPTE ST 2082-1 (12G-SDI) video transport equipment requiring precise genlock and frame-rate conversion.

IC Role / Device Role / Timing Role: Multi-format clock synthesizer generating 74.25 MHz (12G-SDI), 27 MHz (SDI), 48 kHz audio sample clock, and 10 MHz reference from single crystal input.

Use Value: Independent phase adjustment (<20 ps step) enables sub-pixel timing alignment across video pipelines; zero-ppm synthesis avoids long-term drift in broadcast master clocks.

Use Scenario: High-end adaptive computing platform using Xilinx Versal or Intel Agilex FPGAs with heterogeneous clock domains (PL, PS, transceivers, memory interfaces).

IC Role / Device Role / Timing Role: Centralized clock hub supplying LVDS clocks to PL fabric, HCSL to GTY transceivers, SSTL to DDR4 controllers, and CMOS to microcontroller subsystems.

Use Value: Per-output voltage and format configurability eliminates external level translators; I²C programmability enables runtime reconfiguration during partial reconfiguration sequences.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5338A-B05007-GM	Same silicon die and pinout; differs only in factory-programmed NVM configuration (predefined frequency plan).	Pre-configured for fixed frequencies; lacks field-programmability of SI5338N-B05007-GM's blank OTP.	Select SI5338N-B05007-GM when custom frequency plans or post-manufacture I²C reprogramming are required.
LMK04832RHAT	Two PLLs (not four independent MultiSynths); higher power (120 mA vs. 45 mA typ); larger 48-QFN package (7×7 mm).	Optimized for ultra-low jitter (<0.1 ps) in RF/data converter apps; less flexible for multi-frequency, multi-format routing.	Choose LMK04832RHAT only when sub-0.2 ps RMS jitter is mandatory and board space allows larger footprint.

Compared with Si5338A-B05007-GM, SI5338N-B05007-GM offers full field programmability via I²C instead of fixed OTP configuration; compared with LMK04832RHAT, it delivers superior integration density and lower power at the cost of slightly higher jitter floor-making it optimal for space-constrained, multi-protocol digital systems.

Availability

SI5338N-B05007-GM is available at Aetrix Electronics and suitable for Ethernet switch/router timing, PCIe Gen 4 clock distribution, and FPGA clock management applications requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.

Supply support for SI5338N-B05007-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5338 product line was designed to replace multiple discrete oscillators with a single, software-configurable clock generator for high-speed digital systems-targeting PCIe, Ethernet, broadcast, and FPGA-based platforms where flexibility, low jitter, and small footprint are critical.

FAQ

What is the primary function of the SI5338N-B05007-GM in a timing architecture?

The SI5338N-B05007-GM serves as an I²C-programmable quad clock generator that synthesizes four independent, low-jitter output clocks from a single reference input. It replaces up to four discrete oscillators in systems like Ethernet switches and PCIe motherboards, enabling flexible frequency planning, mixed-signal format support, and zero-ppm accuracy via MultiSynth™ fractional-N synthesis.

Does the SI5338N-B05007-GM support PCIe Gen 4 timing requirements?

Yes, the SI5338N-B05007-GM meets PCIe Gen 4 Common Clock jitter specifications (0.15–0.45 ps RMS) when configured for 100 MHz HCSL output. It also complies with PCIe Gen 3 SRNS (0.11–0.32 ps RMS) and supports Gen 1/2/3/4 via its programmable PLL bandwidth and output format flexibility-verified per Skyworks AN562 and PCIe Base Spec 4.0 rev. 0.5.

How many output formats does the SI5338N-B05007-GM support, and can they be mixed simultaneously?

The SI5338N-B05007-GM supports six output formats-LVPECL, LVDS, HCSL, CMOS, SSTL, and HSTL-and all four outputs can be independently configured to different formats and voltages (1.5/1.8/2.5/3.3 V per VDDOx rail). This enables direct interfacing with heterogeneous devices (e.g., 1.8 V FPGA fabric + 3.3 V PHY) without external level shifters.

What is the significance of the "N" suffix in SI5338N-B05007-GM?

The "N" in SI5338N-B05007-GM denotes a blank one-time-programmable (OTP) memory version, meaning the device ships unconfigured and requires I²C programming via ClockBuilder Pro or custom firmware. This contrasts with "A"-suffix variants (e.g., Si5338A-B05007-GM), which contain factory-programmed frequency plans and are not field-reprogrammable.

Can the SI5338N-B05007-GM generate frequencies above 350 MHz on all four outputs simultaneously?

No. The SI5338N-B05007-GM supports up to two unique frequencies above 350 MHz simultaneously-specifically Fvco/4 and Fvco/6-due to VCO frequency division constraints. Outputs above 350 MHz must share these two division ratios; other outputs are limited to ≤350 MHz (LVPECL/LVDS/CML), ≤250 MHz (HCSL), or ≤200 MHz (CMOS) per Skyworks datasheet Table 6.

SI5338N-B05007-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tray

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338N-B05007-GM FAQ

1.How can I place an order for SI5338N-B05007-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338N-B05007-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338N-B05007-GM reliable?

The price and inventory of SI5338N-B05007-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338N-B05007-GM is usually 5 days.

3.What payment methods are accepted for SI5338N-B05007-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338N-B05007-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338N-B05007-GM?

SI5338N-B05007-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338N-B05007-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338N-B05007-GM?

For technical support, including SI5338N-B05007-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338N-B05007-GM requirements.

6.How does Aetrix verify that SI5338N-B05007-GM is sourced from the original manufacturer or authorized distributors?

All SI5338N-B05007-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338N-B05007-GM meets industry standards.

7.What is the process for return or replacement of SI5338N-B05007-GM?

All SI5338N-B05007-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338N-B05007-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338N-B05007-GM part is unused and in its original packaging.

Return procedure for SI5338N-B05007-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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