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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338N-B05007-GMR

Name: SI5338N-B05007-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338N-B05007-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338N-B05007-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338N-B05007-GMR.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5338N-B05007-GMR from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation across –40 to +85 °C. It replaces up to four crystal oscillators in high-speed serial interface timing applications.

For engineers reviewing the SI5338N-B05007-GMR datasheet, SI5338N-B05007-GMR pinout, SI5338N-B05007-GMR application, or SI5338N-B05007-GMR equivalent, key selection criteria include its MultiSynth™-based any-frequency synthesis (0.16–710 MHz per output), independent output voltage control (1.5/1.8/2.5/3.3 V), spread-spectrum capability (0.5–5.0% down-spread), and 24-QFN package compatibility with PCIe, Ethernet, and FPGA clocking systems.

Technical Context

The SI5338N-B05007-GMR implements a two-stage PLL architecture: a high-stability reference stage (with crystal or external clock input) followed by four independent MultiSynth™ fractional-N synthesizers, each driving a configurable output buffer. This enables true zero-ppm frequency accuracy on all four outputs simultaneously.

It supports flexible input references - including 8–30 MHz crystals, 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL, and 5–710 MHz differential inputs - and delivers programmable phase offset (<20 ps steps), glitchless frequency increment/decrement (1 ppm steps), and loss-of-lock/loss-of-signal alarms for system-level timing integrity monitoring.

Key Specifications

Parameter	Value and Actual Design Meaning
Output Count & Type	4 independent outputs; configurable as LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL/CML
Frequency Range	0.16–710 MHz per output; integer/fractional synthesis with 1 ppb resolution
Phase Jitter (RMS)	0.7 ps typical (12 kHz–20 MHz); compliant with PCIe Gen 3 SRNS and Gen 4 Common Clock
Supply Voltages	Core: 1.8/2.5/3.3 V; Output buffers: independently selectable 1.5/1.8/2.5/3.3 V
Input Reference Options	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz)
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch, exposed thermal pad
Operating Temperature	–40 °C to +85 °C ambient; qualified for industrial and telecom line card environments

Pinout & Package

SI5338N-B05007-GMR is housed in a 24-lead QFN package (4 × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin assignments are standardized across the Si5338 family per Skyworks Rev. 1.6 datasheet, page 37.

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2, IN5, IN6	Differential clock inputs	Accept AC-coupled 5–710 MHz differential reference clocks; require external 100 Ω termination
IN3, IN4	Single-ended clock inputs	Support DC-coupled CMOS/SSTL/HSTL inputs (5–350 MHz); VIH = 0.7×VDD, VIL = 0.3×VDD
CLK0A–CLK3B	Differential output pairs	Four fully independent output drivers; each pair configurable for LVPECL/LVDS/HCSL/CML
VDDO0–VDDO3	Output buffer supplies	Independent 1.5/1.8/2.5/3.3 V supply pins per output bank; enable mixed-voltage system interfacing
VDD	Core supply	Single 1.8/2.5/3.3 V core supply; PSRR optimized for low-noise timing performance
SCL, SDA	I²C interface	SMBus-compatible 100/400 kHz interface; supports in-system programming and dynamic reconfiguration
INTR	Interrupt output	Open-drain status indicator for loss-of-lock, loss-of-signal, or configuration error events

Key Features

Feature	Design Value
MultiSynth™ synthesis engine	Enables independent, any-frequency generation on all four outputs with true zero-ppm accuracy and <20 ps phase step resolution
PCIe Gen 1–4 timing compliance	Meets Common Clock jitter requirements (≤0.45 ps RMS for Gen 4) and SRNS spec for Gen 3 without external filtering
Flexible output configuration	Each output supports format (LVDS/LVPECL/HCSL/CMOS/SSTL/HSTL), voltage (1.5–3.3 V), and slew rate tuning - no external level shifters required
Spread-spectrum clocking (SSC)	Configurable per-output: 5–350 MHz range, 0.5–5.0% spread depth, 33–63 kHz modulation rate - reduces EMI in dense PCB layouts
Glitchless frequency tuning	Hardware pin-controlled frequency increment/decrement in 1 ppm steps with sub-1 µs update time - enables real-time clock margining

Applications

PCIe Gen 4 Switch Timing	Ethernet Switch Clocking
Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe Gen 4 switch ASICs in a data center fabric. IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent, low-jitter 100 MHz HCSL clocks with matched skew and SRNS-compliant jitter. Use Value: Eliminates need for four discrete oscillators; ensures Gen 4 link training success via <0.32 ps RMS jitter and deterministic phase alignment across lanes.	Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1G/10G/25G Ethernet PHYs and MACs in a carrier-grade switch. IC Role / Device Role / Timing Role: Any-frequency synthesizer producing three precise frequencies from a single 25 MHz crystal reference using independent MultiSynth™ engines. Use Value: Reduces BOM count and layout area while maintaining IEEE 802.3 jitter compliance (≤1 ps RMS) across all Ethernet rates.
FPGA-Based Video Processing	Telecom Line Card Synchronization
Use Scenario: Supplying pixel clock (148.5 MHz), DDR memory clock (400 MHz), and video processing core clock (300 MHz) to an FPGA in broadcast video equipment. IC Role / Device Role / Timing Role: Configurable quad clock generator with mixed-output formats: LVDS for pixel clock, HCSL for DDR, and CMOS for logic domain. Use Value: Single-chip solution eliminates inter-clock skew and simplifies power sequencing; independent VDDO pins allow optimal voltage per load type.	Use Scenario: Delivering synchronous 2.048 MHz, 19.44 MHz, and 155.52 MHz clocks to T1/E1 framers, SONET/SDH PHYs, and packet processors in a telecom line card. IC Role / Device Role / Timing Role: Precision timing IC supporting OC-12/OC-48 jitter specs (≤0.7 ps RMS) and holdover stability via crystal-referenced PLL. Use Value: Meets GR-1244-CORE and ITU-T G.823/G.8262 requirements without external jitter cleaners or dual-loop architectures.

PCIe Gen 4 Switch Timing

Ethernet Switch Clocking

Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe Gen 4 switch ASICs in a data center fabric.

IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent, low-jitter 100 MHz HCSL clocks with matched skew and SRNS-compliant jitter.

Use Value: Eliminates need for four discrete oscillators; ensures Gen 4 link training success via <0.32 ps RMS jitter and deterministic phase alignment across lanes.

Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1G/10G/25G Ethernet PHYs and MACs in a carrier-grade switch.

IC Role / Device Role / Timing Role: Any-frequency synthesizer producing three precise frequencies from a single 25 MHz crystal reference using independent MultiSynth™ engines.

Use Value: Reduces BOM count and layout area while maintaining IEEE 802.3 jitter compliance (≤1 ps RMS) across all Ethernet rates.

FPGA-Based Video Processing

Telecom Line Card Synchronization

Use Scenario: Supplying pixel clock (148.5 MHz), DDR memory clock (400 MHz), and video processing core clock (300 MHz) to an FPGA in broadcast video equipment.

IC Role / Device Role / Timing Role: Configurable quad clock generator with mixed-output formats: LVDS for pixel clock, HCSL for DDR, and CMOS for logic domain.

Use Value: Single-chip solution eliminates inter-clock skew and simplifies power sequencing; independent VDDO pins allow optimal voltage per load type.

Use Scenario: Delivering synchronous 2.048 MHz, 19.44 MHz, and 155.52 MHz clocks to T1/E1 framers, SONET/SDH PHYs, and packet processors in a telecom line card.

IC Role / Device Role / Timing Role: Precision timing IC supporting OC-12/OC-48 jitter specs (≤0.7 ps RMS) and holdover stability via crystal-referenced PLL.

Use Value: Meets GR-1244-CORE and ITU-T G.823/G.8262 requirements without external jitter cleaners or dual-loop architectures.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D05089-GM	Higher integration: includes integrated LDOs, enhanced jitter performance (0.35 ps RMS), and support for JESD204B deterministic latency	Targeted at JESD204B ADC/DAC synchronization and 5G wireless infrastructure where sub-0.5 ps jitter and deterministic delay are mandatory	Choose Si5332A-D05089-GM when ultra-low jitter and deterministic latency outweigh cost and footprint constraints
ICS853S02IAGLF	Fixed-frequency, non-programmable quad LVDS buffer; no synthesis capability; 1.2 ps RMS jitter; 32-pin TQFP package	Suitable only for fixed-ratio fanout or translation from a master clock - cannot synthesize arbitrary frequencies	Choose ICS853S02IAGLF only when design uses static clock trees and requires lowest possible unit cost with no frequency flexibility

Compared with Si5332A-D05089-GM and ICS853S02IAGLF, the SI5338N-B05007-GMR uniquely balances field-programmability, PCIe Gen 4 compliance, and industrial temperature support in a compact 4×4 mm QFN - making it optimal for reconfigurable, multi-standard timing in space-constrained networking and embedded systems.

Availability

SI5338N-B05007-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, Ethernet switch clocking, and FPGA-based video processing requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for SI5338N-B05007-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and mobile markets.

The Si5338 product line was designed for high-performance, software-configurable clock generation in multi-standard serial interfaces - enabling consolidation of discrete oscillators and simplifying timing architecture in networking, computing, and telecom equipment.

FAQ

What is the maximum output frequency supported by SI5338N-B05007-GMR?

The SI5338N-B05007-GMR supports up to 710 MHz on LVPECL/LVDS/CML outputs, 350 MHz on SSTL/HSTL, 250 MHz on HCSL, and 200 MHz on CMOS outputs. Frequencies above 350 MHz are limited to two unique values simultaneously (Fvco/4 and Fvco/6) due to VCO architecture constraints, as specified in the Si5338 datasheet Section 3.3.

Does SI5338N-B05007-GMR support PCIe Gen 4 Common Clock compliance?

Yes, the SI5338N-B05007-GMR meets PCIe Gen 4 Common Clock jitter requirements with ≤0.45 ps RMS (10 kHz–50 MHz) when configured per Skyworks AN562 guidelines. Its measured 0.15–0.45 ps RMS jitter under Gen 4 test conditions confirms compliance without external jitter cleaning circuitry.

Can SI5338N-B05007-GMR generate different output voltages on each channel?

Yes, SI5338N-B05007-GMR provides independent VDDO0–VDDO3 supply pins, allowing each of its four output banks to be powered at 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This enables direct interfacing with mixed-voltage devices (e.g., 1.8 V FPGA I/O and 3.3 V legacy PHYs) without external level translators.

How is SI5338N-B05007-GMR programmed in-system?

The SI5338N-B05007-GMR is programmed via its I²C/SMBus-compatible interface (SCL/SDA pins) operating at up to 400 kHz. Configuration is typically performed using Skyworks' ClockBuilder Pro software, which generates register maps and supports real-time frequency/phase adjustments without device reset.

What crystal frequency ranges does SI5338N-B05007-GMR support?

The SI5338N-B05007-GMR supports external crystals from 8 MHz to 30 MHz in four bands: 8–11 MHz, 11–19 MHz, 19–26 MHz, and 26–30 MHz. Each band has defined load capacitance (11–13 pF supported, 17–19 pF recommended) and ESR limits (≤300 Ω max), per Tables 8–11 of the Si5338 datasheet Rev. 1.6.

SI5338N-B05007-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338N-B05007-GMR FAQ

1.How can I place an order for SI5338N-B05007-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338N-B05007-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338N-B05007-GMR reliable?

The price and inventory of SI5338N-B05007-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338N-B05007-GMR is usually 5 days.

3.What payment methods are accepted for SI5338N-B05007-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338N-B05007-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338N-B05007-GMR?

SI5338N-B05007-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338N-B05007-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338N-B05007-GMR?

For technical support, including SI5338N-B05007-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338N-B05007-GMR requirements.

6.How does Aetrix verify that SI5338N-B05007-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338N-B05007-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338N-B05007-GMR meets industry standards.

7.What is the process for return or replacement of SI5338N-B05007-GMR?

All SI5338N-B05007-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338N-B05007-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338N-B05007-GMR part is unused and in its original packaging.

Return procedure for SI5338N-B05007-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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