Skyworks Solutions Inc. SI5338N-B05025-GM
- Part No.:
- SI5338N-B05025-GM
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Application Specific Clock/Timing
- Package:
- 24-VFQFN Exposed Pad
- Datasheet:
-
SI5338N-B05025-GM.pdf
- Description:
- I2C CONTROL, 4-OUTPUT, ANY FREQU
- Quantity:
- Payment:

- Shipping:

Inventory:1,979
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SI5338N-B05025-GM from Skyworks Solutions is a quad-output, I²C-programmable clock generator with MultiSynth™ frequency synthesis. It delivers four independent, any-frequency outputs (0.16–710 MHz), supports LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats, achieves 0.7 ps RMS phase jitter, and operates from 1.8/2.5/3.3 V core supply in PCIe Gen 1–4 and Ethernet timing applications.
For engineers reviewing the SI5338N-B05025-GM datasheet, SI5338N-B05025-GM pinout, SI5338N-B05025-GM application, or SI5338N-B05025-GM equivalent, key selection criteria include differential output jitter performance, per-output voltage configurability (1.5–3.3 V), independent phase/frequency adjustment (±45 ns / 1 ppm steps), spread-spectrum control (0.5–5.0% at 33–63 kHz), and 24-QFN package compatibility with PCIe SRNS and broadcast video timing requirements.
Technical Context
The SI5338N-B05025-GM implements a two-stage PLL architecture: a high-stability reference stage (with crystal or external clock input) followed by four independent MultiSynth™ fractional-N synthesizers. Each synthesizer drives one of four configurable output drivers, enabling true zero-ppm frequency accuracy across all outputs without shared dividers.
It supports flexible input references - including 8–30 MHz crystals, 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL, and 5–710 MHz differential signals - and provides loss-of-lock and loss-of-signal alarms, external feedback for zero-delay mode, and I²C/SMBus programming with ClockBuilder Pro software integration.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output count & type | 4 differential clock outputs (CLK0A/B to CLK3A/B); supports mixed single-ended/differential configurations up to 8 total clocks |
| Frequency range | 0.16–710 MHz per output; integer/fractional synthesis with 1 ppb resolution |
| Phase jitter (RMS) | 0.7 ps typical (12 kHz–20 MHz); compliant with PCIe Gen 3 SRNS and GbE jitter specs |
| Supply voltages | Core: 1.8/2.5/3.3 V ±10%; output buffers: independently configurable 1.5/1.8/2.5/3.3 V |
| Operating temperature | –40 °C to +85 °C ambient; qualified for industrial and telecom line card environments |
| Package | 24-pin QFN, 4 mm × 4 mm, 0.5 mm pitch; exposed thermal pad for thermal management |
| Control interface | I²C/SMBus-compatible serial interface; supports ClockBuilder Pro configuration and pin-controlled frequency/phase update |
Pinout & Package
SI5338N-B05025-GM is housed in a 24-lead, 4 mm × 4 mm QFN package with exposed thermal pad. Pin assignments are fixed per the Si5338 family and validated for this variant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN1, IN2 | Differential reference input pair | Accepts 5–710 MHz AC-coupled differential clock; requires external 100 Ω termination |
| IN3, IN4 | Single-ended reference inputs | Support 5–200 MHz CMOS-level clocks; VIH = 0.7×VDD, VIL = 0.3×VDD |
| CLK0A, CLK0B – CLK3A, CLK3B | Differential clock outputs | Four independent pairs; each configurable for LVPECL/LVDS/HCSL/CML with per-driver VDDO |
| VDDO0–VDDO3 | Output buffer supply pins | Enable independent voltage setting (1.5–3.3 V) per output driver group |
| VDD | Core supply | 1.8/2.5/3.3 V ±10%; PSRR optimized for low-noise clock generation |
| SCL, SDA | I²C serial interface | Standard SMBus-compatible bus; supports 400 kHz fast-mode operation |
| INTR | Interrupt output | Open-drain status indicator for loss-of-lock and loss-of-signal events |
| GND, RSVD_GND | Ground connections | Multiple dedicated ground pins plus reserved ground pad for EMI reduction and thermal dissipation |
Key Features
| Feature | Design Value |
|---|---|
| Independent per-output frequency synthesis | Each of four outputs generates any frequency from 0.16–710 MHz with zero ppm error using MultiSynth™ |
| Programmable phase offset | ±45 ns adjustment in <20 ps steps per output; enables precise inter-clock alignment in multi-FPGA systems |
| Glitchless frequency tuning | 1 ppm increment/decrement via pin or I²C; no output interruption during dynamic reconfiguration |
| Configurable spread spectrum | 0.5–5.0% down-spread at 33–63 kHz on any output; reduces EMI without affecting timing margins |
| PCIe Gen 4 Common Clock compliance | 0.15–0.45 ps RMS jitter (10 kHz–50 MHz); meets PCIe Base Spec 4.0 rev 0.5 jitter mask requirements |
| External feedback support | Enables zero-delay mode for synchronous clock distribution in backplane or daisy-chain topologies |
Applications
| PCIe Gen 4 Switch Timing | Ethernet Switch/Routing |
|---|---|
Use Scenario: High-speed switch ASIC requiring synchronized 100 MHz HCSL clocks for multiple SerDes lanes with strict jitter limits. IC Role / Device Role / Timing Role: Primary clock generator providing four independent PCIe-compliant reference clocks with SRNS validation. Use Value: 0.15 ps RMS jitter ensures compliance with PCIe Gen 4 Common Clock specification; independent outputs eliminate need for multiple oscillators. |
Use Scenario: 10 GbE line card needing low-jitter 156.25 MHz and 312.5 MHz clocks for PHY and MAC layers. IC Role / Device Role / Timing Role: Quad-output synthesizer delivering differential LVDS clocks with programmable phase alignment between data paths. Use Value: Sub-1 ps RMS jitter and <100 ps output-to-output skew enable deterministic latency in packet forwarding pipelines. |
| Broadcast Video Timing | FPGA-Based Processor Clocking |
Use Scenario: SMPTE ST 2082-1 12G-SDI transmitter requiring stable 27 MHz, 74.25 MHz, and 148.5 MHz clocks with tight phase coherence. IC Role / Device Role / Timing Role: Any-frequency clock generator producing exact video standard frequencies from a single crystal reference. Use Value: True zero-ppm synthesis eliminates frame sync drift; independent phase control aligns pixel clock edges across parallel video streams. |
Use Scenario: Xilinx Versal or Intel Agilex FPGA board needing multiple domain clocks (e.g., 100 MHz system, 250 MHz transceiver, 500 MHz DDR). IC Role / Device Role / Timing Role: Configurable clock source supporting mixed signal formats (LVDS, HCSL, CMOS) and voltage levels per FPGA bank. Use Value: Per-output VDDO (1.5–3.3 V) and format selection simplify PCB routing and eliminate level-shifter components. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad-output programmable clock generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5332A-D05025-GM | Higher integration: 8 outputs, integrated LDOs, lower jitter (0.35 ps RMS), but larger 32-QFN package | Better suited for dense multi-ASIC boards where space permits and ultra-low jitter is critical | Select when >4 outputs or sub-0.5 ps jitter required; not drop-in due to pin count and power architecture differences |
| ICS8430I-01LG | Fixed-frequency, non-programmable quad LVDS generator; 0.9 ps RMS jitter; 3.3 V only; no I²C interface | Limited to static clock trees; lacks frequency/phase flexibility and spread-spectrum capability | Choose for cost-sensitive, unchanging clock architectures where programmability is unnecessary |
Compared with Si5332A-D05025-GM and ICS8430I-01LG, the SI5338N-B05025-GM uniquely balances field-programmability, jitter performance, and compact 24-QFN footprint-making it optimal for PCIe Gen 4, broadcast video, and FPGA platforms requiring design flexibility without layout overhaul.
Availability
SI5338N-B05025-GM is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, 10 GbE routing infrastructure, and broadcast video equipment requiring stable component supply, long-term lifecycle support, and traceable sourcing.
Supply support for SI5338N-B05025-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.
The Si5338 product line was designed to replace multiple discrete oscillators with a single, software-configurable clock generator for high-performance computing, networking, and media infrastructure applications.
FAQ
What is the maximum output frequency supported by SI5338N-B05025-GM?
The SI5338N-B05025-GM supports up to 710 MHz on LVPECL/LVDS/CML outputs, 350 MHz on SSTL/HSTL, 250 MHz on HCSL, and 200 MHz on CMOS. Frequencies above 350 MHz require use of Fvco/4 or Fvco/6 synthesis paths, limiting simultaneous high-frequency outputs to two unique values.
Does SI5338N-B05025-GM support PCIe Gen 4 Common Clock compliance?
Yes, SI5338N-B05025-GM meets PCIe Gen 4 Common Clock jitter requirements with 0.15–0.45 ps RMS (10 kHz–50 MHz) when configured per Skyworks AN562 guidelines. Its PLL bandwidth (2–5 MHz) and output format (HCSL) are validated for Intel Clock Jitter Tool v1.6.4 testing.
Can SI5338N-B05025-GM generate different output voltages simultaneously?
Yes, SI5338N-B05025-GM provides four independent VDDO pins (VDDO0–VDDO3), allowing each output driver group to operate at 1.5 V, 1.8 V, 2.5 V, or 3.3 V concurrently-enabling direct interfacing with mixed-voltage FPGAs, ASICs, and PHYs without external level shifters.
How is SI5338N-B05025-GM programmed in-system?
SI5338N-B05025-GM uses an I²C/SMBus-compatible serial interface (SCL/SDA) for full register configuration. Skyworks ClockBuilder Pro software generates custom configuration files, which are loaded via I²C during initialization or runtime-supporting both EEPROM-based boot and dynamic reprogramming.
What is the thermal performance of SI5338N-B05025-GM in continuous operation?
SI5338N-B05025-GM has a junction-to-ambient thermal resistance (θJA) of 37 °C/W under still-air conditions. With its exposed thermal pad properly soldered to a PCB copper plane, it sustains full 4-output operation at 85 °C ambient while maintaining jitter and frequency stability within datasheet limits.
SI5338N-B05025-GM Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- MultiSynth™
- Package/Case:
- 24-VFQFN Exposed Pad
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- PLL:
- -
- Main Purpose:
- -
- Input:
- -
- Output:
- -
- Number of Circuits:
- -
- Ratio - Input:Output:
- -
- Differential - Input:Output:
- -
- Frequency - Max:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 24-QFN (4x4)
SI5338N-B05025-GM FAQ
1.How can I place an order for SI5338N-B05025-GM through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5338N-B05025-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5338N-B05025-GM reliable?
The price and inventory of SI5338N-B05025-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338N-B05025-GM is usually 5 days.
3.What payment methods are accepted for SI5338N-B05025-GM?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338N-B05025-GM transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5338N-B05025-GM?
SI5338N-B05025-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5338N-B05025-GM order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5338N-B05025-GM?
For technical support, including SI5338N-B05025-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338N-B05025-GM requirements.
6.How does Aetrix verify that SI5338N-B05025-GM is sourced from the original manufacturer or authorized distributors?
All SI5338N-B05025-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338N-B05025-GM meets industry standards.
7.What is the process for return or replacement of SI5338N-B05025-GM?
All SI5338N-B05025-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338N-B05025-GM, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5338N-B05025-GM part is unused and in its original packaging.
Return procedure for SI5338N-B05025-GM:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SI5338N-B05025-GM Tags

-
LMK00334RTVRQ1
Texas Instruments
.jpg)
-
DSC557-0344FI0T
Microchip Technology

-
9FGV0241AKILFT
Renesas

-
9DBL0452CKILFT
Renesas
.jpg)
-
DSC557-0344FL1T
Microchip Technology
-
RC19008AGND#KB0
Renesas
-
RC19008AGND#BB0
Renesas

-
9DB403DGILFT
Renesas

-
9DB233AGILFT
Renesas

-
9DB803DGILFT
Renesas

-
9FGL0851DKILFT
Renesas
-
AB-557-03-HCHC-F-L-C-T
Abracon LLC
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

