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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338N-B05026-GMR

Name: SI5338N-B05026-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338N-B05026-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338N-B05026-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338N-B05026-GMR.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5338N-B05026-GMR from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation from 1.8/2.5/3.3 V core supply in a 4 × 4 mm 24-QFN package. It replaces up to four crystal oscillators in high-speed serial interface timing applications.

For engineers reviewing the SI5338N-B05026-GMR datasheet, SI5338N-B05026-GMR pinout, SI5338N-B05026-GMR application, or SI5338N-B05026-GMR equivalent, key selection criteria include output format flexibility (LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL), independent per-output voltage (1.5–3.3 V), any-frequency synthesis down to 0.16 MHz, spread-spectrum capability (0.5–5.0% spread), and glitchless frequency adjustment in 1 ppm steps.

Technical Context

The SI5338N-B05026-GMR implements a two-stage PLL architecture: a reference-stage PLL locks to one of six input sources (crystal, CMOS, SSTL/HSTL, or differential), followed by four independent MultiSynth™ fractional-N synthesizers - each driving a dedicated output stage. This enables true zero-ppm frequency accuracy across all four outputs simultaneously.

Each output driver supports programmable signal format, output voltage (1.5/1.8/2.5/3.3 V), phase offset (±45 ns in <20 ps steps), and spread-spectrum modulation (33–63 kHz rate, 0.5–5.0% depth). Input-to-output propagation delay is 2.5–4 ns in buffer mode, and loss-of-signal/loss-of-lock alarms are provided via the INTR pin.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 3 SRNS & Gen 4 common clock jitter requirements
Output Frequency Range	0.16–710 MHz per channel; LVPECL/LVDS up to 710 MHz, HCSL up to 250 MHz, CMOS up to 200 MHz
Input Reference Support	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz)
Supply Voltages	Core: 1.8/2.5/3.3 V ±10%; Output buffers: independently configurable 1.5/1.8/2.5/3.3 V
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch; RoHS-compliant, halogen-free, moisture sensitivity level 3
Operating Temperature	–40 °C to +85 °C ambient; qualified per industrial-grade reliability standards
Power Consumption	45 mA typical core current at 100 MHz on all outputs and 25 MHz reference clock

Pinout & Package

SI5338N-B05026-GMR is housed in a 24-lead, 4 × 4 mm QFN package with exposed thermal pad. Pin assignments follow the standard Si5338 top-view layout: pins 1–24 include six input clocks (IN1–IN6), four differential output pairs (CLK0A/B through CLK3A/B), four VDDOx supplies (VDDO0–VDDO3), dual VDD core supplies, SCL/SDA/I²C interface, INTR alarm output, and reserved ground (RSVD_GND).

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2, IN5, IN6	Differential input pair	Accept AC-coupled differential clock (5–710 MHz); require external 100 Ω termination
IN3, IN4	Single-ended input	Accept DC-coupled CMOS/SSTL/HSTL (5–350 MHz); VIH = 0.7×VDD, VIL = 0.3×VDD
CLK0A–CLK3B	Differential output pairs	Four independent LVPECL/LVDS/HCSL/CML outputs; each with programmable format, voltage, and phase
VDDO0–VDDO3	Output buffer supply	Independent 1.5/1.8/2.5/3.3 V supplies per output bank; decoupling required per datasheet
SCL, SDA	I²C interface	Standard SMBus-compatible 100/400 kHz interface for configuration and status readback
INTR	Interrupt output	Open-drain active-low alarm indicating loss-of-signal or loss-of-lock condition

Key Features

Feature	Design Value
MultiSynth™ synthesis	Four independent fractional-N synthesizers enabling any-frequency output (0.16–710 MHz) with 0 ppm error
Glitchless frequency tuning	Independent ±1 ppm step increment/decrement via pin control or I²C, with update time ≤667 ns
Programmable phase alignment	Per-output phase offset adjustable in <20 ps steps over ±45 ns range for skew-sensitive systems
Spread-spectrum clocking	Configurable SSC on any output: 5–350 MHz frequency, 0.5–5.0% spread depth, 33–63 kHz modulation rate
PCIe Gen 4 compliance	Meets PCIe Base Spec 4.0 common clock jitter requirement (≤0.45 ps RMS, 10 kHz–50 MHz)
Zero-delay mode support	External feedback path enables synchronous clock distribution with minimal latency and deterministic skew

Applications

PCIe Gen 4 Switch Timing	Ethernet Switch Clocking
Use Scenario: Providing synchronized, low-jitter reference clocks to multiple PCIe Gen 4 switch ASICs in a data center fabric. IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent 100 MHz HCSL clocks with matched phase and sub-0.45 ps RMS jitter. Use Value: Enables full Gen 4 link training and stable 16 GT/s operation without retiming or jitter cleanup ICs.	Use Scenario: Generating multi-rate clocks (125 MHz, 156.25 MHz, 312.5 MHz) for 1/10/25 GbE switch PHYs and MACs. IC Role / Device Role / Timing Role: Any-frequency synthesizer producing precise Ethernet line rates from a single 25 MHz crystal reference. Use Value: Eliminates need for multiple crystals or discrete PLLs; reduces BOM count and board area by >60%.
Broadcast Video Sync Generator	FPGA Processor Clocking
Use Scenario: Delivering SMPTE ST 2082 (12G-SDI) and ST 2081 (6G-SDI) reference clocks in broadcast video routers. IC Role / Device Role / Timing Role: Low-phase-noise clock generator providing 27 MHz, 74.25 MHz, and 148.5 MHz LVDS outputs with <10 ps pk-pk period jitter. Use Value: Ensures frame-accurate synchronization across multi-channel video processing pipelines with no visible artifacts.	Use Scenario: Supplying core, I/O, and transceiver clocks to Xilinx Versal or Intel Agilex FPGAs in adaptive compute platforms. IC Role / Device Role / Timing Role: Configurable quad clock source supporting mixed-voltage FPGA banks (1.0 V core, 1.8 V I/O, 0.9 V transceivers). Use Value: Allows dynamic reconfiguration of clock frequencies and formats via I²C during FPGA partial reconfiguration.

PCIe Gen 4 Switch Timing

Ethernet Switch Clocking

Use Scenario: Providing synchronized, low-jitter reference clocks to multiple PCIe Gen 4 switch ASICs in a data center fabric.

IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent 100 MHz HCSL clocks with matched phase and sub-0.45 ps RMS jitter.

Use Value: Enables full Gen 4 link training and stable 16 GT/s operation without retiming or jitter cleanup ICs.

Use Scenario: Generating multi-rate clocks (125 MHz, 156.25 MHz, 312.5 MHz) for 1/10/25 GbE switch PHYs and MACs.

IC Role / Device Role / Timing Role: Any-frequency synthesizer producing precise Ethernet line rates from a single 25 MHz crystal reference.

Use Value: Eliminates need for multiple crystals or discrete PLLs; reduces BOM count and board area by >60%.

Broadcast Video Sync Generator

FPGA Processor Clocking

Use Scenario: Delivering SMPTE ST 2082 (12G-SDI) and ST 2081 (6G-SDI) reference clocks in broadcast video routers.

IC Role / Device Role / Timing Role: Low-phase-noise clock generator providing 27 MHz, 74.25 MHz, and 148.5 MHz LVDS outputs with <10 ps pk-pk period jitter.

Use Value: Ensures frame-accurate synchronization across multi-channel video processing pipelines with no visible artifacts.

Use Scenario: Supplying core, I/O, and transceiver clocks to Xilinx Versal or Intel Agilex FPGAs in adaptive compute platforms.

IC Role / Device Role / Timing Role: Configurable quad clock source supporting mixed-voltage FPGA banks (1.0 V core, 1.8 V I/O, 0.9 V transceivers).

Use Value: Allows dynamic reconfiguration of clock frequencies and formats via I²C during FPGA partial reconfiguration.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D05026-GM	Higher integration: includes integrated crystal, smaller 3 × 3 mm 24-QFN, lower power (32 mA typ), but fixed 4-output LVDS-only configuration	Limited to LVDS outputs; no HCSL/CMOS/SSTL support; not suitable for PCIe Gen 4 HCSL or mixed-format systems	Select when board space and power are critical and output format is uniform LVDS only.
ICS8430I-01LG	Non-programmable, fixed-frequency quad LVDS generator; no I²C interface; 1.2 ps RMS jitter; requires external crystal oscillator	No frequency or format flexibility; cannot synthesize arbitrary frequencies; lacks spread spectrum or phase adjustment	Select for cost-sensitive, static-clock applications where design reuse of legacy fixed-frequency timing is required.

Compared with Si5332A-D05026-GM and ICS8430I-01LG, the SI5338N-B05026-GMR uniquely supports full I²C programmability, mixed-signal-format outputs, and PCIe Gen 4-compliant jitter performance - making it the only option for dynamically reconfigurable, multi-standard timing in next-gen switches and adaptive compute platforms.

Availability

SI5338N-B05026-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, Ethernet 10/25/100 GbE infrastructure, broadcast video synchronization, and FPGA-based adaptive compute platforms requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for SI5338N-B05026-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for communications, automotive, and industrial markets.

The Si5338 family is designed as a programmable, high-performance clock generator platform targeting high-speed serial interfaces - specifically engineered to replace multiple discrete oscillators and simplify timing architecture in PCIe, Ethernet, and broadcast video systems.

FAQ

What is the maximum output frequency supported by SI5338N-B05026-GMR in LVPECL mode?

The SI5338N-B05026-GMR supports LVPECL output frequencies up to 710 MHz. This capability is confirmed in Table 6 of the official Skyworks datasheet Rev. 1.6, which specifies 550–710 MHz as a valid LVPECL frequency band under defined test conditions. Operation above 350 MHz is limited to two unique frequencies simultaneously (Fvco/4 and Fvco/6) due to internal VCO constraints.

Does SI5338N-B05026-GMR support PCIe Gen 4 Common Clock compliance?

Yes, SI5338N-B05026-GMR meets PCIe Gen 4 Common Clock jitter requirements: ≤0.45 ps RMS (10 kHz–50 MHz) as verified in Table 12 of the Skyworks datasheet Rev. 1.6. This compliance is achieved using a PLL bandwidth of 2–4 MHz or 2–5 MHz with CDR = 10 MHz, and applies to 100 MHz HCSL outputs - the standard format used in PCIe Gen 4 root complexes and switches.

Can SI5338N-B05026-GMR generate different output formats simultaneously?

Yes, SI5338N-B05026-GMR supports simultaneous mixed-format outputs: for example, CLK0A/B as LVDS, CLK1A/B as HCSL, CLK2A/B as CMOS, and CLK3A/B as SSTL. Each output driver is independently configurable for format, voltage (1.5/1.8/2.5/3.3 V), and termination, as detailed in Section 3.4 "Output Stage" and Table 6 of the datasheet.

What is the minimum input crystal frequency supported by SI5338N-B05026-GMR?

The SI5338N-B05026-GMR supports external crystals from 8 MHz to 30 MHz, as specified in Tables 8–11 of the Skyworks datasheet Rev. 1.6. The lowest validated crystal frequency is 8 MHz (with 11–13 pF load capacitance support), and operation below this range is not guaranteed or characterized.

How is phase alignment controlled across the four outputs of SI5338N-B05026-GMR?

SI5338N-B05026-GMR provides independent programmable phase offset on each output, adjustable in <20 ps steps over a ±45 ns range (POFFSET register, Table 5). Phase alignment is maintained across temperature and voltage via on-chip calibration, and skew between outputs is guaranteed ≤100 ps (tDSKEW) when using identical dividers and formats.

SI5338N-B05026-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338N-B05026-GMR FAQ

1.How can I place an order for SI5338N-B05026-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338N-B05026-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338N-B05026-GMR reliable?

The price and inventory of SI5338N-B05026-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338N-B05026-GMR is usually 5 days.

3.What payment methods are accepted for SI5338N-B05026-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338N-B05026-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338N-B05026-GMR?

SI5338N-B05026-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338N-B05026-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338N-B05026-GMR?

For technical support, including SI5338N-B05026-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338N-B05026-GMR requirements.

6.How does Aetrix verify that SI5338N-B05026-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338N-B05026-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338N-B05026-GMR meets industry standards.

7.What is the process for return or replacement of SI5338N-B05026-GMR?

All SI5338N-B05026-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338N-B05026-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338N-B05026-GMR part is unused and in its original packaging.

Return procedure for SI5338N-B05026-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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