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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338N-B05066-GM

Name: SI5338N-B05066-GM
Brand: Skyworks Solutions Inc.
SKU: SI5338N-B05066-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338N-B05066-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338N-B05066-GM.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

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Product details

Overview

SI5338N-B05066-GM from Skyworks Solutions is a quad-output, I²C-programmable clock generator using MultiSynth™ technology to synthesize any frequency on each of four independent differential outputs (CLK0A/B through CLK3A/B), with 0 ppm precision, 0.7 ps RMS typical phase jitter, and support for LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats across 0.16–710 MHz. It serves as a PCIe Gen 1–4 common clock source in high-speed switch/router and FPGA timing systems.

For engineers reviewing the SI5338N-B05066-GM datasheet, SI5338N-B05066-GM pinout, SI5338N-B05066-GM application, or SI5338N-B05066-GM equivalent, key selection criteria include its 24-QFN package, independent per-output voltage control (1.5/1.8/2.5/3.3 V), PCIe Gen 3 SRNS compliance, spread-spectrum capability (0.5–5.0% at 33–63 kHz), and I²C/SMBus programmability with ClockBuilder Pro software integration.

Technical Context

The SI5338N-B05066-GM implements a two-stage synthesis architecture: a PLL-based Stage 1 (with 1.6 MHz loop bandwidth) locks to one of six input references (crystal, CMOS, SSTL/HSTL, or differential), followed by four independent MultiSynth™ fractional-N dividers (Stage 2) generating output frequencies with sub-ppb resolution. Each output driver supports format and voltage configuration without shared constraints.

It features loss-of-lock and loss-of-signal alarms, independent phase adjustment (<20 ps steps), glitchless frequency increment/decrement (1 ppm steps), and external feedback mode for zero-delay operation - all managed via a single I²C interface with register-based configuration stored in OTP NVM.

Key Specifications

Parameter	Value and Actual Design Meaning
Output Count & Type	Four differential pairs (CLK0A/B–CLK3A/B); supports up to eight single-ended clocks or mixed configurations
Frequency Range	0.16–710 MHz per output; LVPECL/LVDS up to 710 MHz, HCSL up to 250 MHz, CMOS up to 200 MHz
Phase Jitter (RMS)	0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 3 SRNS and Gen 4 common clock specs
Input Flexibility	Supports 8–30 MHz crystal, 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL, or 5–710 MHz differential reference
Supply & Power	1.8/2.5/3.3 V core supply; 45 mA typical core current; independent VDDOx per output (1.5–3.3 V)
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch, exposed thermal pad
Operating Temp	–40 °C to +85 °C ambient; qualified for industrial and telecom line card environments

Pinout & Package

SI5338N-B05066-GM uses a 24-lead QFN package (4 mm × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin assignments are fixed per the Si5338 family and validated for this variant.

Pin/Terminal	Circuit Role	Design Meaning
IN1/IN2, IN5/IN6	Differential Input Pairs	Accept 5–710 MHz AC-coupled differential clocks; require external 100 Ω termination
IN3/IN4	Single-Ended Inputs	Support 5–200 MHz CMOS clocks; VIH = 0.7×VDD, VIL = 0.3×VDD
CLK0A/CLK0B – CLK3A/CLK3B	Differential Output Pairs	Configurable per-output format/voltage; each pair shares no electrical coupling
VDDO0–VDDO3	Output Buffer Supplies	Independent 1.4–3.63 V supplies per output bank; enable level translation
VDD	Core Supply	1.8/2.5/3.3 V ± tolerance; powers PLL, synthesis logic, and I²C interface
SCL/SDA	I²C Interface	Standard SMBus-compatible serial bus (up to 400 kHz); supports ClockBuilder Pro programming
INTR	Interrupt Output	Open-drain status signal indicating loss-of-lock or loss-of-signal events

Key Features

Feature	Design Value
MultiSynth™ Synthesis	Four independent fractional-N synthesizers enabling true zero-ppm accuracy on all outputs simultaneously
PCIe Compliance	Fully compliant with PCIe Gen 1/2/3/4 Common Clock and Gen 3 SRNS jitter requirements
Flexible Output Configuration	Per-output selection of LVPECL, LVDS, HCSL, CMOS, SSTL, or HSTL with independent VDDO voltage
Glitchless Frequency Tuning	Hardware-supported frequency increment/decrement in 1 ppm steps without output interruption
Spread Spectrum Control	Programmable SSC on any output: 0.5–5.0% spread, 33–63 kHz modulation rate, configurable direction
Zero-Delay Mode	External feedback path enables synchronous clock distribution with minimal propagation delay

Applications

PCIe Gen 4 Switch Timing	Ethernet Switch Clocking
Use Scenario: High-density 10/25/100 GbE switch ASIC requiring low-jitter, multi-frequency reference clocks for SerDes lanes and management subsystems. IC Role / Device Role / Timing Role: Primary clock generator providing four synchronized, independently configured outputs - two at 100 MHz (HCSL) for PCIe Gen 4 root complex, two at 156.25 MHz (LVDS) for Ethernet PHYs. Use Value: Meets PCIe Gen 4 common clock TJ < 33.6 ps pk-pk and 100GBASE-KR4 jitter budgets while eliminating discrete oscillator count and board space.	Use Scenario: Carrier-grade Ethernet aggregation switch needing deterministic clock alignment across multiple line cards and backplane interfaces. IC Role / Device Role / Timing Role: Centralized timing hub distributing 125 MHz (LVDS), 156.25 MHz (HCSL), and 312.5 MHz (LVPECL) clocks with sub-100 ps skew between outputs. Use Value: Achieves <100 ps output-output skew and 0.7 ps RMS jitter - critical for IEEE 1588 PTP timestamp accuracy and SERDES CDR lock stability.
FPGA-Based Video Processing	Telecom Line Card Synchronization
Use Scenario: Broadcast video encoder/decoder platform using Xilinx Ultrascale+ FPGA with multiple clock domains (video pixel, AXI, GTY transceivers). IC Role / Device Role / Timing Role: Quad-output generator supplying 74.25 MHz (LVDS) for HDMI video, 100 MHz (LVDS) for AXI interconnect, 125 MHz (HCSL) for 10GbE MAC, and 156.25 MHz (LVPECL) for GTY transceivers. Use Value: Eliminates need for four separate oscillators; enables dynamic reconfiguration via I²C during mode switching without hardware change.	Use Scenario: OTN/SDH line card requiring synchronization to Stratum 3E reference while generating multiple tributary clocks (e.g., 155.52 MHz, 622.08 MHz, 2.488 GHz). IC Role / Device Role / Timing Role: Frequency translator and jitter cleaner accepting 19.44 MHz Stratum 3E input and generating OC-12/OC-48/OC-192 clocks with <0.7 ps RMS jitter. Use Value: Replaces legacy PLL+VCXO solutions with integrated MultiSynth™, reducing BOM count and improving holdover stability via internal NVM configuration.

PCIe Gen 4 Switch Timing

Ethernet Switch Clocking

Use Scenario: High-density 10/25/100 GbE switch ASIC requiring low-jitter, multi-frequency reference clocks for SerDes lanes and management subsystems.

IC Role / Device Role / Timing Role: Primary clock generator providing four synchronized, independently configured outputs - two at 100 MHz (HCSL) for PCIe Gen 4 root complex, two at 156.25 MHz (LVDS) for Ethernet PHYs.

Use Value: Meets PCIe Gen 4 common clock TJ < 33.6 ps pk-pk and 100GBASE-KR4 jitter budgets while eliminating discrete oscillator count and board space.

Use Scenario: Carrier-grade Ethernet aggregation switch needing deterministic clock alignment across multiple line cards and backplane interfaces.

IC Role / Device Role / Timing Role: Centralized timing hub distributing 125 MHz (LVDS), 156.25 MHz (HCSL), and 312.5 MHz (LVPECL) clocks with sub-100 ps skew between outputs.

Use Value: Achieves <100 ps output-output skew and 0.7 ps RMS jitter - critical for IEEE 1588 PTP timestamp accuracy and SERDES CDR lock stability.

FPGA-Based Video Processing

Telecom Line Card Synchronization

Use Scenario: Broadcast video encoder/decoder platform using Xilinx Ultrascale+ FPGA with multiple clock domains (video pixel, AXI, GTY transceivers).

IC Role / Device Role / Timing Role: Quad-output generator supplying 74.25 MHz (LVDS) for HDMI video, 100 MHz (LVDS) for AXI interconnect, 125 MHz (HCSL) for 10GbE MAC, and 156.25 MHz (LVPECL) for GTY transceivers.

Use Value: Eliminates need for four separate oscillators; enables dynamic reconfiguration via I²C during mode switching without hardware change.

Use Scenario: OTN/SDH line card requiring synchronization to Stratum 3E reference while generating multiple tributary clocks (e.g., 155.52 MHz, 622.08 MHz, 2.488 GHz).

IC Role / Device Role / Timing Role: Frequency translator and jitter cleaner accepting 19.44 MHz Stratum 3E input and generating OC-12/OC-48/OC-192 clocks with <0.7 ps RMS jitter.

Use Value: Replaces legacy PLL+VCXO solutions with integrated MultiSynth™, reducing BOM count and improving holdover stability via internal NVM configuration.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-A05189-GM	Higher integration: includes integrated crystal, lower jitter (0.35 ps RMS), supports up to 10 outputs, but larger 32-QFN package	Better suited for space-constrained designs where crystal omission and ultra-low jitter are prioritized over cost and footprint	Select when system-level jitter budget is <0.5 ps RMS and crystal placement is impractical
ICS853S02AGT	Fixed-frequency, non-programmable quad LVDS buffer; no synthesis, no I²C, no spread spectrum; 1.2 ps RMS jitter	Limited to static clock fanout; cannot replace multiple crystals or perform frequency translation	Choose only for simple clock distribution where frequency agility and PCIe compliance are not required

Compared with Si5332A-A05189-GM, SI5338N-B05066-GM offers lower cost, smaller 24-QFN footprint, and field-programmability without integrated crystal dependency; versus ICS853S02AGT, it provides full frequency synthesis, PCIe compliance, and dynamic reconfiguration - making it suitable for adaptive timing architectures.

Availability

SI5338N-B05066-GM is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, Ethernet switch clocking, and FPGA-based video processing requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for SI5338N-B05066-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and mobile markets.

The Si5338 product line was designed specifically for high-performance, multi-protocol timing in datacenter switches, telecom line cards, and FPGA-based systems - emphasizing programmability, low jitter, and flexible output formatting.

FAQ

What is the primary function of the SI5338N-B05066-GM in a PCIe Gen 4 system?

The SI5338N-B05066-GM serves as a common clock generator delivering four low-jitter, independently configurable outputs - typically two at 100 MHz (HCSL) for PCIe Gen 4 root complex and endpoint links. Its 0.7 ps RMS jitter and PCIe Gen 4 common clock compliance ensure reliable CDR lock and meet TJ < 33.6 ps pk-pk requirements. SI5338N-B05066-GM replaces multiple discrete oscillators while supporting dynamic reconfiguration via I²C during system initialization or power-state transitions.

Does the SI5338N-B05066-GM support spread-spectrum clocking (SSC), and how is it configured?

Yes, the SI5338N-B05066-GM supports programmable spread-spectrum clocking on any output: spread range 0.5–5.0%, modulation rate 33–63 kHz, and selectable up/down/center-spread direction. Configuration is performed via I²C registers using ClockBuilder Pro software or direct register writes. SSC is applied post-synthesis and does not affect frequency accuracy - it reduces EMI peaks without compromising timing integrity. SI5338N-B05066-GM implements SSC independently per output, allowing selective application to noise-sensitive interfaces only.

Can the SI5338N-B05066-GM operate without an external crystal?

Yes, the SI5338N-B05066-GM can operate without an external crystal by accepting alternative reference inputs: CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), or differential (5–710 MHz) signals on dedicated input pins. When using an external crystal, it supports 8–30 MHz fundamental-mode crystals with on-chip load capacitance tuning. SI5338N-B05066-GM's flexibility eliminates crystal dependency in systems with existing clean reference clocks - such as those derived from network synchronizers or recovered SerDes clocks.

How does the SI5338N-B05066-GM handle loss-of-signal (LOS) detection?

The SI5338N-B05066-GM monitors all six input pins (IN1–IN6) for loss-of-signal conditions with configurable thresholds and response times: LOS detect time is 2.6–5 µs, and release time is 0.01–1 µs. Detection status is reported via the open-drain INTR pin and readable in status registers. SI5338N-B05066-GM supports automatic failover to alternate inputs or output freeze modes upon LOS, ensuring deterministic behavior in redundant clock architectures. This functionality is active in both PLL and bypass modes.

Is the SI5338N-B05066-GM pin-compatible with other Si5338 variants?

Yes, all Si5338 variants - including SI5338N-B05066-GM - share identical 24-QFN pinout, package dimensions, and thermal pad layout. Differences between variants (e.g., B05066 vs. A05189) relate solely to factory-programmed NVM content, default configuration, and supported frequency ranges - not physical or electrical pin behavior. SI5338N-B05066-GM maintains full PCB compatibility across the Si5338 family, enabling design reuse and simplified inventory management.

SI5338N-B05066-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tray

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338N-B05066-GM FAQ

1.How can I place an order for SI5338N-B05066-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338N-B05066-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338N-B05066-GM reliable?

The price and inventory of SI5338N-B05066-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338N-B05066-GM is usually 5 days.

3.What payment methods are accepted for SI5338N-B05066-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338N-B05066-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338N-B05066-GM?

SI5338N-B05066-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338N-B05066-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338N-B05066-GM?

For technical support, including SI5338N-B05066-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338N-B05066-GM requirements.

6.How does Aetrix verify that SI5338N-B05066-GM is sourced from the original manufacturer or authorized distributors?

All SI5338N-B05066-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338N-B05066-GM meets industry standards.

7.What is the process for return or replacement of SI5338N-B05066-GM?

All SI5338N-B05066-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338N-B05066-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338N-B05066-GM part is unused and in its original packaging.

Return procedure for SI5338N-B05066-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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