Skyworks Solutions Inc. SI5338N-B05066-GMR

Overview

SI5338N-B05066-GMR from Skyworks Solutions is a quad-output, I²C-programmable clock generator with MultiSynth™ frequency synthesis. It delivers four independent, any-frequency outputs (0.16–710 MHz), supports LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats, achieves 0.7 ps RMS phase jitter, and operates from 1.8/2.5/3.3 V core supply in PCIe Gen 4–compliant timing systems for FPGA and processor clocking.

For engineers reviewing the SI5338N-B05066-GMR datasheet, SI5338N-B05066-GMR pinout, SI5338N-B05066-GMR application, or SI5338N-B05066-GMR equivalent, key selection criteria include differential output jitter performance, I²C configurability across four independent drivers, PCIe Gen 4 SRNS compliance, and support for external crystal (8–30 MHz) or high-frequency differential inputs (up to 710 MHz).

Technical Context

The SI5338N-B05066-GMR implements a two-stage PLL architecture: a reference-stage PLL locks to an input clock (crystal, CMOS, or differential), followed by four independent MultiSynth™ fractional-N synthesizers per output channel. Each synthesizer provides zero-ppm frequency accuracy and supports integer or fractional mode operation with programmable phase offset (±45 ns) and glitchless frequency adjustment in 1 ppm steps.

It features fully independent output buffers with per-driver voltage selection (1.5/1.8/2.5/3.3 V), configurable spread-spectrum modulation (0.5–5.0% spread, 33–63 kHz rate), loss-of-lock and loss-of-signal alarms, and I²C/SMBus interface with ClockBuilder Pro software support. The device operates across –40 to +85 °C and meets PCIe Gen 1/2/3/4 Common Clock and Gen 3 SRNS specifications.

Key Specifications

Pinout & Package

The SI5338N-B05066-GMR is housed in a 24-lead, 4 × 4 mm QFN package with exposed thermal pad. Pin assignments are fixed per Skyworks Si5338 family specification and validated for this variant.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output clock generator applications.

Compared with Si5338A-B05083-GM and LMK04832RHAT, the SI5338N-B05066-GMR offers optimal balance of low jitter (0.7 ps RMS), compact 4×4 mm QFN packaging, and full I²C configurability - making it ideal for space-constrained, multi-protocol systems where PCIe Gen 4, Ethernet, and broadcast timing coexist.

Availability

SI5338N-B05066-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 server backplanes, FPGA-based broadcast video equipment, Ethernet switch line cards, and industrial processor clocking requiring stable component supply and long-term lifecycle assurance.

Supply support for SI5338N-B05066-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for communications, automotive, and industrial markets.

The Si5338 product line was engineered to replace multiple discrete oscillators with a single programmable clock generator - targeting high-performance computing, networking, and broadcast infrastructure where flexibility, low jitter, and small footprint are critical.

FAQ

What is the primary function of the SI5338N-B05066-GMR in a timing architecture?

The SI5338N-B05066-GMR serves as a quad-output, I²C-programmable clock generator that synthesizes four independent, any-frequency clocks (0.16–710 MHz) from a single reference. Its MultiSynth™ architecture enables zero-ppm accuracy per output, supporting PCIe Gen 4, 10 GbE, and broadcast video timing without external jitter cleaners. SI5338N-B05066-GMR replaces up to four discrete oscillators while maintaining sub-1 ps RMS jitter performance.

Does the SI5338N-B05066-GMR support PCIe Gen 4 timing requirements?

Yes, the SI5338N-B05066-GMR meets PCIe Gen 4 common clock jitter specifications with ≤0.45 ps RMS (12 kHz–20 MHz) when configured per Skyworks' validated test setup. It is also compliant with PCIe Gen 3 SRNS (≤0.32 ps RMS) and Gen 1/2/3 common clock standards. SI5338N-B05066-GMR achieves this using its low-noise PLL architecture, optimized loop bandwidth (2–5 MHz), and differential output drivers.

Can the SI5338N-B05066-GMR generate different output voltage levels simultaneously?

Yes, the SI5338N-B05066-GMR supports independent output buffer supplies (VDDO0–VDDO3), allowing each of its four output banks to operate at 1.5 V, 1.8 V, 2.5 V, or 3.3 V concurrently. This enables direct interfacing with mixed-voltage devices - such as 1.8 V FPGAs, 2.5 V SerDes, and 3.3 V microcontrollers - without external level shifters. SI5338N-B05066-GMR's per-bank voltage control is hardware-configurable and retained across power cycles.

What input reference sources does the SI5338N-B05066-GMR accept?

The SI5338N-B05066-GMR accepts multiple reference types: an 8–30 MHz fundamental-mode crystal connected to IN1/IN2; single-ended CMOS clocks (5–200 MHz) on IN3/IN4; or differential inputs (5–710 MHz) on IN1/IN2 or IN5/IN6. It also supports external feedback for zero-delay mode. SI5338N-B05066-GMR's flexible input stage eliminates need for external buffers or translators in most system designs.

How is the SI5338N-B05066-GMR programmed and configured?

The SI5338N-B05066-GMR is configured via its I²C/SMBus-compatible serial interface (SCL/SDA pins), supporting standard-mode (100 kHz) and fast-mode (400 kHz) operation. Skyworks' ClockBuilder Pro software generates register maps and .c files for custom configurations. SI5338N-B05066-GMR also supports pin-controlled frequency increment/decrement and programmable initial phase offset (±45 ns) for runtime adjustments without host intervention.