Skyworks Solutions Inc. SI5338N-B05167-GMR
- Part No.:
- SI5338N-B05167-GMR
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Application Specific Clock/Timing
- Package:
- 24-VFQFN Exposed Pad
- Datasheet:
-
SI5338N-B05167-GMR.pdf
- Description:
- I2C CONTROL, 4-OUTPUT, ANY FREQU
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SI5338N-B05167-GMR from Skyworks Solutions is an I²C-programmable quad clock generator IC with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation across –40 to +85 °C. It replaces up to four crystal oscillators in high-speed serial interface timing applications such as PCIe switch cards and FPGA-based compute platforms.
For engineers reviewing the SI5338N-B05167-GMR datasheet, SI5338N-B05167-GMR pinout, SI5338N-B05167-GMR application, or SI5338N-B05167-GMR equivalent, key selection considerations include its MultiSynth™ fractional-N synthesis architecture, per-output voltage control (1.5/1.8/2.5/3.3 V), independent phase/frequency adjustment (±45 ns / 1 ppm steps), and support for input references from 5 MHz to 710 MHz.
Technical Context
The SI5338N-B05167-GMR implements a two-stage PLL architecture: a high-stability integer-N Phase-Locked Loop (Stage 1) locks to one of six input sources (crystal, CMOS, SSTL/HSTL, or differential), followed by four independent MultiSynth™ fractional-N synthesis blocks (Stage 2) generating output clocks with 1 ppb frequency resolution. Each output driver supports LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats.
It features loss-of-lock and loss-of-signal monitoring, programmable spread spectrum (0.5–5.0% deviation, 33–63 kHz modulation), external feedback mode for zero-delay operation, and glitchless frequency increment/decrement via dedicated pins or I²C. Core supply operates at 1.8/2.5/3.3 V with 45 mA typical current draw.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Phase Jitter (RMS) | 0.7 ps - meets PCIe Gen 3 SRNS and Gen 4 common clock jitter requirements for 100 MHz HCSL outputs |
| Output Count & Type | 4 differential outputs (CLK0A/B–CLK3A/B) - supports up to eight single-ended clocks via configurable drivers |
| Frequency Range | 0.16–710 MHz - covers PCIe 100 MHz, Ethernet 125/156.25 MHz, Fibre Channel 1.0625 GHz (via Fvco/4), and processor reference clocks |
| Input Reference Support | Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz) - enables flexible system-level clock tree design |
| Supply Voltages | VDD = 1.8/2.5/3.3 V ±10%; VDDOx = 1.4–3.63 V - allows independent output voltage setting per driver for mixed-voltage SoC/FPGA interfaces |
| Operating Temperature | –40 to +85 °C - qualified for industrial and telecom line card environments without derating |
| Package | 24-pin QFN, 4 × 4 mm - surface-mount compatible with standard reflow profiles and IPC-7351B land pattern |
Pinout & Package
SI5338N-B05167-GMR is housed in a 24-lead, 4 × 4 mm QFN package with exposed thermal pad. Pin assignments follow Skyworks' standard Si5338 pinout: dual differential inputs (IN1/IN2, IN5/IN6), two single-ended inputs (IN3, IN4), four differential output pairs (CLK0A/B–CLK3A/B), three independent VDDO supplies (VDDO0–VDDO3), core VDD, I²C interface (SCL/SDA), interrupt (INTR), and reserved ground (RSVD_GND).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN1 / IN2 | Differential Input Pair 1 | Accepts 5–710 MHz AC-coupled differential clock; internal 100 Ω termination enabled |
| IN3 / IN4 | Single-Ended Input Pins | Support CMOS/SSTL/HSTL inputs (5–350 MHz); VIH/VIL referenced to VDD |
| CLK0A / CLK0B | Differential Output Pair 0 | Configurable LVPECL/LVDS/HCSL/CMOS; voltage set by VDDO0 (1.5–3.3 V) |
| CLK1A / CLK1B | Differential Output Pair 1 | Independent frequency/phase/format control; supports same signal standards as CLK0 |
| VDDO0–VDDO3 | Output Buffer Supplies | Enable per-output voltage selection-critical for interfacing with mixed-voltage FPGAs or ASICs |
| SCL / SDA | I²C Interface | SMBus-compatible 100/400 kHz operation; supports ClockBuilder Pro configuration and runtime tuning |
| INTR | Interrupt Output | Open-drain status flag for loss-of-lock, loss-of-signal, or PLL unlock events |
Key Features
| Feature | Design Value |
|---|---|
| MultiSynth™ Synthesis | Four independent fractional-N synthesizers enable true zero-ppm accuracy on all outputs without shared dividers |
| Per-Output Voltage Control | VDDO0–VDDO3 allow simultaneous LVDS (1.8 V), HCSL (1.8 V), and CMOS (3.3 V) outputs on same device |
| Glitchless Frequency Adjustment | Hardware pin-controlled ±1 ppm steps (PINC/FDEC) enable real-time clock rate tuning without output interruption |
| Programmable Phase Offset | ±45 ns range in <20 ps steps permits precise skew alignment between high-speed SerDes lanes |
| Spread Spectrum Clocking | Configurable SSC on any output (5–350 MHz, 0.5–5.0% spread, 33–63 kHz modulation) reduces EMI in dense PCB layouts |
| PCIe Compliance | Fully compliant with PCIe Gen 1/2/3/4 Common Clock and Gen 3 SRNS jitter masks-validated per Intel Clock Jitter Tool v1.6.4 |
Applications
| PCIe Switch Timing | Ethernet Switch Clocking |
|---|---|
Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe Gen 3/4 switches and endpoint devices in a modular server backplane. IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent, low-jitter PCIe-compliant clocks with matched propagation delay and skew control. Use Value: Eliminates need for four discrete oscillators; enables deterministic inter-lane skew compensation via per-output phase adjustment. |
Use Scenario: Generating 125 MHz (1 GbE), 156.25 MHz (10 GbE), and 312.5 MHz (25 GbE) clocks for multi-rate Ethernet PHYs and MACs on a single switch ASIC. IC Role / Device Role / Timing Role: Any-frequency synthesizer supporting IEEE 802.3 standards with sub-1 ps RMS jitter and spread spectrum capability. Use Value: Reduces EMI in high-density switch PCBs while meeting stringent jitter budgets for 10/25 GbE CDR lock stability. |
| FPGA Processor Clocking | Broadcast Video Timing |
Use Scenario: Supplying core, memory, and I/O clocks to Xilinx Versal or Intel Agilex FPGAs requiring multiple voltage domains and precise phase relationships. IC Role / Device Role / Timing Role: Configurable buffer and level translator with independent VDDO supplies and format flexibility (LVDS, HCSL, CMOS). Use Value: Simplifies board-level clock distribution by replacing discrete buffers and level shifters while maintaining <10 ps cycle-cycle jitter. |
Use Scenario: Delivering SMPTE ST 2059-2–compliant 27 MHz, 74.25 MHz, and 148.5 MHz video reference clocks to SDI transmitters, frame synchronizers, and color correctors. IC Role / Device Role / Timing Role: High-precision frequency translator converting GPS-disciplined 10 MHz OCXO input to broadcast-grade video frequencies. Use Value: Achieves <0.1 ppm long-term accuracy and <1 ps RMS jitter required for genlock stability in 4K/8K production systems. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad clock generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5332A-D05167-GM | Higher integration: 8 outputs, integrated EEPROM, lower jitter (0.35 ps RMS), supports JESD204B deterministic latency | Targeted at JESD204B data converter timing and multi-channel RF systems where deterministic latency matters | Select when >4 outputs, ultra-low jitter, or deterministic latency are required; not drop-in due to different pinout and register map |
| ICS853S01AGI-01LFT | Fixed-function 4-output LVDS clock fanout buffer; no frequency synthesis, no I²C, 1.2 ps RMS jitter | Used only for clock distribution-not generation-where input frequency matches output requirements exactly | Choose only for simple fanout applications with no frequency translation; lacks programmability, spread spectrum, or multi-format support |
Compared with SI5338N-B05167-GMR, the Si5332 offers higher performance and density but requires redesign; the ICS853S01AGI-01LFT provides lower cost for static fanout but cannot synthesize arbitrary frequencies or adapt to changing system clock needs.
Availability
SI5338N-B05167-GMR is available at Aetrix Electronics and suitable for PCIe switch timing, Ethernet switch clocking, and FPGA processor clocking requiring stable component supply, full traceability, and long-term lifecycle support.
Supply support for SI5338N-B05167-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and industrial markets.
The Si5338 product line delivers programmable, low-jitter clock generation for high-speed serial interfaces-including PCIe, Ethernet, and Fibre Channel-enabling flexible, space-efficient timing architectures in next-generation compute and networking equipment.
FAQ
What is the primary function of the SI5338N-B05167-GMR in a timing architecture?
The SI5338N-B05167-GMR serves as an I²C-programmable quad clock generator that synthesizes four independent, low-jitter output frequencies from a single input reference. Its MultiSynth™ architecture enables true zero-ppm accuracy on each output, making it ideal for replacing multiple fixed-frequency oscillators in PCIe, Ethernet, and FPGA-based systems. SI5338N-B05167-GMR supports both frequency translation and buffer-mode operation.
Does the SI5338N-B05167-GMR support PCIe Gen 4 timing requirements?
Yes, the SI5338N-B05167-GMR meets PCIe Gen 4 common clock jitter specifications with ≤0.45 ps RMS (1.5–50 MHz band) when configured per Skyworks' validated settings. It is explicitly listed as PCIe Gen 1/2/3/4 Common Clock and Gen 3 SRNS compliant in the official datasheet, and jitter validation was performed using the Intel Clock Jitter Tool v1.6.4. SI5338N-B05167-GMR achieves this with its optimized PLL loop bandwidth and low-noise MultiSynth™ synthesis.
Can the SI5338N-B05167-GMR generate different output voltages simultaneously?
Yes, the SI5338N-B05167-GMR supports independent output supply voltages via VDDO0–VDDO3 pins, enabling simultaneous LVDS (1.8 V), HCSL (1.8 V), and CMOS (3.3 V) outputs on the same device. Each output driver's voltage is set by its dedicated VDDO rail, allowing direct interface with mixed-voltage FPGAs, ASICs, or SerDes PHYs without external level shifters. This capability is confirmed in Table 6 and Section 3.4 of the datasheet.
How is the SI5338N-B05167-GMR programmed and configured?
The SI5338N-B05167-GMR is programmed via an I²C/SMBus-compatible serial interface operating at 100/400 kHz. Configuration is simplified using Skyworks' ClockBuilder Pro software, which generates custom configuration files and registers settings based on user-defined frequency plans. SI5338N-B05167-GMR also supports hardware pin control for real-time frequency increment/decrement and output enable/disable functions without host intervention.
What package type and thermal characteristics does the SI5338N-B05167-GMR have?
The SI5338N-B05167-GMR uses a 24-pin QFN package measuring 4 × 4 mm with an exposed thermal pad. Its thermal resistance is θJA = 37 °C/W (still air) and θJC = 10 °C/W, enabling reliable operation at full load across –40 to +85 °C ambient. The package complies with JEDEC J-STD-020 reflow profiles and is compatible with standard IPC-7351B land patterns. SI5338N-B05167-GMR's low 45 mA typical core current further reduces thermal load.
SI5338N-B05167-GMR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- MultiSynth™
- Package/Case:
- 24-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- PLL:
- -
- Main Purpose:
- -
- Input:
- -
- Output:
- -
- Number of Circuits:
- -
- Ratio - Input:Output:
- -
- Differential - Input:Output:
- -
- Frequency - Max:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 24-QFN (4x4)
SI5338N-B05167-GMR FAQ
1.How can I place an order for SI5338N-B05167-GMR through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5338N-B05167-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5338N-B05167-GMR reliable?
The price and inventory of SI5338N-B05167-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338N-B05167-GMR is usually 5 days.
3.What payment methods are accepted for SI5338N-B05167-GMR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338N-B05167-GMR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5338N-B05167-GMR?
SI5338N-B05167-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5338N-B05167-GMR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5338N-B05167-GMR?
For technical support, including SI5338N-B05167-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338N-B05167-GMR requirements.
6.How does Aetrix verify that SI5338N-B05167-GMR is sourced from the original manufacturer or authorized distributors?
All SI5338N-B05167-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338N-B05167-GMR meets industry standards.
7.What is the process for return or replacement of SI5338N-B05167-GMR?
All SI5338N-B05167-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338N-B05167-GMR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5338N-B05167-GMR part is unused and in its original packaging.
Return procedure for SI5338N-B05167-GMR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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