Skyworks Solutions Inc. SI5338N-B05168-GM
- Part No.:
- SI5338N-B05168-GM
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Application Specific Clock/Timing
- Package:
- 24-VFQFN Exposed Pad
- Datasheet:
-
SI5338N-B05168-GM.pdf
- Description:
- I2C CONTROL, 4-OUTPUT, ANY FREQU
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SI5338N-B05168-GM from Skyworks Solutions is a quad-output, I²C-programmable clock generator implementing MultiSynth™ frequency synthesis with 0 ppm precision per output, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and support for LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL outputs up to 710 MHz. It replaces multiple crystal oscillators in high-speed serial interface timing applications such as PCIe root complexes and FPGA clock trees.
For engineers reviewing the SI5338N-B05168-GM datasheet, SI5338N-B05168-GM pinout, SI5338N-B05168-GM application, or SI5338N-B05168-GM equivalent, key selection criteria include differential output jitter performance at 125 MHz (0.7 ps RMS), independent per-output voltage configuration (1.5/1.8/2.5/3.3 V), and programmable phase/frequency adjustment in <20 ps / 1 ppm steps - all validated for industrial temperature range (–40 to +85 °C).
Technical Context
The SI5338N-B05168-GM integrates a fractional-N PLL with two-stage MultiSynth™ synthesis: first-stage PLL locks to an input reference (crystal, CMOS, or differential, 5–710 MHz), then four independent MultiSynth™ dividers generate precise output frequencies. Each output driver supports format- and voltage-selectable signaling with dedicated VDDO supplies.
It features loss-of-lock and loss-of-signal detection, external feedback mode for zero-delay operation, and I²C/SMBus-compatible configuration via 24-pin QFN package. The device operates from a single 1.8/2.5/3.3 V core supply with 45 mA typical current draw and supports spread-spectrum clocking (0.5–5.0% spread, 33–63 kHz modulation) on any output.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Count | Four independent differential or single-ended clock outputs (CLK0A/B through CLK3A/B) |
| Phase Jitter (RMS) | 0.7 ps typical (12 kHz–20 MHz), enabling PCIe Gen 4 and 10 GbE timing compliance |
| Frequency Range | 0.16–710 MHz per output; supports integer/fractional synthesis with 1 ppb resolution |
| Input Reference | Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz) |
| Supply Voltages | Core: 1.8/2.5/3.3 V ±10%; Output buffers: independently configurable 1.5/1.8/2.5/3.3 V |
| Operating Temp | –40 to +85 °C ambient, qualified for industrial embedded and telecom line card use |
| Package | 24-pin QFN, 4 × 4 mm, 0.5 mm pitch, exposed thermal pad |
Pinout & Package
SI5338N-B05168-GM uses a 24-pin QFN (4 × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are defined per Skyworks Rev. 1.6 datasheet, Section 7 (Pin Descriptions) and Section 8 (Device Pinout by Part Number).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN1, IN2, IN5, IN6 | Differential input pairs | Accept AC-coupled differential clocks up to 710 MHz; require external 100 Ω termination |
| IN3, IN4 | Single-ended input pins | Support CMOS/SSTL/HSTL inputs (5–350 MHz); VIH = 0.7×VDD, VIL = 0.3×VDD |
| CLK0A–CLK3B | Differential clock outputs | Eight terminals forming four differential pairs; each pair independently format- and voltage-configurable |
| VDDO0–VDDO3 | Output buffer supplies | Independent 1.5/1.8/2.5/3.3 V supplies per output bank; enable mixed-voltage system interfacing |
| VDD | Core supply | Single 1.8/2.5/3.3 V supply powering PLL, logic, and memory; PSRR optimized |
| SCL, SDA | I²C interface | Standard SMBus-compatible 100/400 kHz interface; supports write-protection and register readback |
| INTR | Interrupt output | Open-drain status indicator for loss-of-lock and loss-of-signal alarms |
Key Features
| Feature | Design Value |
|---|---|
| MultiSynth™ synthesis | Enables true zero-ppm frequency accuracy on all four outputs without external crystals or VCXOs |
| Per-output voltage control | Each of four output banks powered by independent VDDO supplies (1.5/1.8/2.5/3.3 V) for direct interfacing with mixed-voltage FPGAs and ASICs |
| Programmable phase offset | ±45 ns initial phase adjustment per output with <20 ps step resolution for skew compensation across parallel data paths |
| Glitchless frequency tuning | Independent frequency increment/decrement (1 ppm steps) via pin or I²C, enabling dynamic rate adaptation without output interruption |
| PCIe Gen 4 compliance | Validated 0.15–0.45 ps RMS jitter in Common Clock mode per PCI-SIG Base Spec 4.0 rev. 0.5 |
| Spread-spectrum clocking | Configurable SSC on any output (0.5–5.0% spread, 33–63 kHz modulation) to reduce EMI in dense PCB layouts |
Applications
| PCIe Root Complex Timing | FPGA/ASIC Clock Distribution |
|---|---|
Use Scenario: Providing synchronized 100 MHz reference clocks to PCIe Gen 3/4 slots and upstream switch in server motherboard designs. IC Role / Device Role / Timing Role: Quad-output clock generator delivering Common Clock architecture-compliant signals with sub-0.45 ps RMS jitter. Use Value: Eliminates need for four discrete oscillators while meeting PCIe Gen 4 jitter mask requirements and supporting dynamic link training. |
Use Scenario: Driving multiple clock domains in Xilinx Versal or Intel Agilex FPGAs requiring LVDS, HCSL, and CMOS clocks at different frequencies. IC Role / Device Role / Timing Role: Programmable multi-format clock source with independent VDDO per output bank for mixed-signaling interfaces. Use Value: Reduces BOM count and layout complexity while enabling precise inter-clock phase alignment for high-speed SerDes and memory interfaces. |
| Ethernet Switch Fabric | Broadcast Video Synchronization |
Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10 GbE PHYs and packet processing ASICs in enterprise switches. IC Role / Device Role / Timing Role: Low-jitter frequency translator converting a 25 MHz crystal reference into multiple Ethernet-compliant rates. Use Value: Achieves <1 ps RMS jitter across all outputs, satisfying IEEE 802.3 clause 40/49 jitter budgets without external cleanup PLLs. |
Use Scenario: Delivering genlock-accurate 27 MHz, 74.25 MHz, and 148.5 MHz clocks to SDI transmitters, video processors, and frame synchronizers in broadcast equipment. IC Role / Device Role / Timing Role: Any-frequency synthesizer with programmable initial phase offset for frame-accurate timing alignment across distributed video nodes. Use Value: Enables sub-100 ps inter-output skew control and zero-ppm frequency stability required for SMPTE ST 2059-2 PTP synchronization. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad-output programmable clock generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5332A-D05168-GM | Higher integration: includes integrated crystal, lower power (32 mA typ), enhanced jitter (0.35 ps RMS), but limited to three outputs | Preferred for space-constrained designs where crystal integration and ultra-low jitter outweigh need for fourth output | Select when board area and jitter margin are critical, and only three outputs are required |
| ICS853S01AGI-01LFT | Fixed-function 4-output LVDS clock generator; no I²C programming, no frequency flexibility, higher jitter (1.2 ps RMS) | Suitable only for static clock trees with fixed frequencies and identical output formats | Choose only for cost-sensitive, non-programmable applications where frequency agility is unnecessary |
Compared with Si5332A-D05168-GM and ICS853S01AGI-01LFT, SI5338N-B05168-GM uniquely balances full I²C programmability, four independent outputs, PCIe Gen 4 compliance, and industrial temperature support - making it optimal for reconfigurable systems requiring field-upgradable timing.
Availability
SI5338N-B05168-GM is available at Aetrix Electronics and suitable for PCIe Gen 4 server motherboards, FPGA-based telecom line cards, and broadcast video infrastructure requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.
Supply support for SI5338N-B05168-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and mobile markets.
The SI5338N-B05168-GM belongs to Skyworks' Si5338 family of any-frequency clock generators, designed specifically for high-speed serial interface timing in datacenter, networking, and broadcast equipment where low jitter, programmability, and multi-format output flexibility are essential.
FAQ
What is the maximum differential output frequency supported by the SI5338N-B05168-GM?
The SI5338N-B05168-GM supports differential output frequencies up to 710 MHz for LVPECL and LVDS, 250 MHz for HCSL, and 350 MHz for CML and SSTL/HSTL. Frequencies above 350 MHz are restricted to two unique values simultaneously (Fvco/4 and Fvco/6) per Skyworks Rev. 1.6 datasheet Table 6.
Does the SI5338N-B05168-GM support PCIe Gen 4 timing requirements?
Yes, the SI5338N-B05168-GM is explicitly validated for PCIe Gen 4 Common Clock mode with 0.15–0.45 ps RMS jitter (10 kHz–50 MHz), compliant with PCI-SIG Base Specification 4.0 rev. 0.5. This is confirmed in Table 12 of the Skyworks Rev. 1.6 datasheet under "PCIe Gen 4, Common Clock".
Can the SI5338N-B05168-GM operate with a single 25 MHz crystal input?
Yes, the SI5338N-B05168-GM accepts external crystals from 8 to 30 MHz, including 25 MHz. It supports on-chip load capacitance tuning (11–13 pF) and accommodates standard 18 pF crystals via register configuration per AN360 application note.
How many independent output voltage supplies does the SI5338N-B05168-GM provide?
The SI5338N-B05168-GM provides four independent output buffer supplies (VDDO0–VDDO3), each configurable for 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This enables simultaneous driving of mixed-voltage devices such as 1.8 V FPGAs and 3.3 V legacy peripherals from a single IC.
Is the SI5338N-B05168-GM pin-compatible with other Si5338 variants?
Yes, all Si5338 variants-including SI5338N-B05168-GM-share the same 24-pin QFN package and pinout per Skyworks Section 8 (Device Pinout by Part Number). Functionality differences (e.g., factory-programmed vs. blank OTP) do not affect mechanical or electrical pin compatibility.
SI5338N-B05168-GM Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- MultiSynth™
- Package/Case:
- 24-VFQFN Exposed Pad
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- PLL:
- -
- Main Purpose:
- -
- Input:
- -
- Output:
- -
- Number of Circuits:
- -
- Ratio - Input:Output:
- -
- Differential - Input:Output:
- -
- Frequency - Max:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 24-QFN (4x4)
SI5338N-B05168-GM FAQ
1.How can I place an order for SI5338N-B05168-GM through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5338N-B05168-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5338N-B05168-GM reliable?
The price and inventory of SI5338N-B05168-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338N-B05168-GM is usually 5 days.
3.What payment methods are accepted for SI5338N-B05168-GM?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338N-B05168-GM transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5338N-B05168-GM?
SI5338N-B05168-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5338N-B05168-GM order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5338N-B05168-GM?
For technical support, including SI5338N-B05168-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338N-B05168-GM requirements.
6.How does Aetrix verify that SI5338N-B05168-GM is sourced from the original manufacturer or authorized distributors?
All SI5338N-B05168-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338N-B05168-GM meets industry standards.
7.What is the process for return or replacement of SI5338N-B05168-GM?
All SI5338N-B05168-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338N-B05168-GM, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5338N-B05168-GM part is unused and in its original packaging.
Return procedure for SI5338N-B05168-GM:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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