Skyworks Solutions Inc. SI5338N-B05168-GMR

Overview

SI5338N-B05168-GMR from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and MultiSynth™ frequency synthesis supporting any output frequency from 0.16 MHz to 710 MHz. It replaces up to four crystal oscillators in high-speed serial interface timing applications such as PCIe root complexes and FPGA clock trees.

For engineers reviewing the SI5338N-B05168-GMR datasheet, SI5338N-B05168-GMR pinout, SI5338N-B05168-GMR application, or SI5338N-B05168-GMR equivalent, key selection criteria include its 24-QFN package, independent per-output voltage (1.5/1.8/2.5/3.3 V), spread-spectrum capability (0.5–5.0% down-spread), glitchless 1 ppm frequency increment/decrement, and <20 ps phase step resolution.

Technical Context

The SI5338N-B05168-GMR implements a two-stage PLL architecture: a high-stability reference stage (with programmable R-divider) feeding a fractional-N MultiSynth™ VCO stage (N-divider), followed by independent P-divider output paths. Each of the four output drivers supports LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats with per-driver supply voltage selection and programmable slew rate control.

It accepts multiple input references - 8–30 MHz crystal, 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL, or 5–710 MHz differential - and provides loss-of-lock and loss-of-signal alarms. External feedback mode enables zero-delay operation, while I²C/SMBus interface allows full register-level configuration including initial phase offset (±45 ns), spread-spectrum modulation rate (33–63 kHz), and SSC deviation (0.5–5.0%).

Key Specifications

Pinout & Package

SI5338N-B05168-GMR is housed in a 4 × 4 mm, 24-lead QFN package with exposed thermal pad. Pin assignments follow the standard Si5338 pinout: dual differential inputs (IN1/IN2, IN5/IN6), single-ended inputs (IN3, IN4), four differential output pairs (CLK0A/B–CLK3A/B), three dedicated output supply rails (VDDO0–VDDO3), core supply (VDD), I²C interface (SCL, SDA), interrupt (INTR), and reserved ground (RSVD_GND).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output programmable clock generator applications.

Compared with Si5338A-B05168-GM, SI5338N-B05168-GMR offers guaranteed factory-programmed configuration enabling immediate operation post-power-up, while ICS853S02IAGLF lacks synthesis, programmability, and PCIe-compliant jitter - making it unsuitable for high-speed serial interface timing.

Availability

SI5338N-B05168-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 server platforms, Ethernet switching infrastructure, and FPGA-based broadcast video systems requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for SI5338N-B05168-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5338 product line delivers highly configurable, low-jitter clock generation for high-speed serial interfaces - designed specifically to replace multiple fixed-frequency oscillators and simplify timing architecture in PCIe, Ethernet, and FPGA-based systems.

FAQ

What is the default startup configuration of the SI5338N-B05168-GMR?

The SI5338N-B05168-GMR ships with factory-programmed OTP memory containing a valid clock configuration. Upon power-up, it begins generating clocks immediately without requiring I²C initialization - unlike blank-OTP variants such as Si5338A-B05168-GM. This behavior is guaranteed per Skyworks datasheet Rev. 1.6, Section 11.2.

Does the SI5338N-B05168-GMR support PCIe Gen 4 Common Clock compliance?

Yes, the SI5338N-B05168-GMR achieves 0.15–0.45 ps RMS jitter (typ) in PCIe Gen 4 Common Clock mode, as verified in Table 12 of the official datasheet. It meets the PCI-SIG Base Specification 4.0 rev. 0.5 requirement when configured with PLL bandwidth 2–4 MHz and CDR = 10 MHz.

Can the SI5338N-B05168-GMR generate frequencies above 350 MHz on all four outputs simultaneously?

No. Per Table 6 and Section 3.3 of the datasheet, only two unique frequencies above 350 MHz can be generated simultaneously - specifically Fvco/4 and Fvco/6. Higher-frequency outputs must share these two synthesis paths, limiting concurrent >350 MHz outputs to two channels on the SI5338N-B05168-GMR.

What is the maximum allowable input slew rate for optimal jitter performance on the SI5338N-B05168-GMR?

For best jitter performance, the differential input slew rate on pins IN1/IN2 and IN5/IN6 must exceed 0.3 V/ns, and the single-ended input slew rate on IN3/IN4 must exceed 1.0 V/ns, as specified in Table 6 Notes 2 and 4. Exceeding these thresholds minimizes deterministic jitter contributions from input edge uncertainty.

How does the SI5338N-B05168-GMR handle loss-of-signal detection?

The SI5338N-B05168-GMR detects loss of signal on any enabled input within 2.6–5 µs (tLOS), and releases the alarm within 0.01–1 µs (tLOSRLS). The status is reported via the open-drain INTR pin and corresponding status registers, enabling fast system-level fault response without host processor intervention.