Skyworks Solutions Inc. SI5338N-B05174-GM

Overview

SI5338N-B05174-GM from Skyworks Solutions is a quad-output, I²C-programmable clock generator implementing MultiSynth™ frequency synthesis with 0 ppm precision per output. It delivers four independent differential or single-ended clocks (LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL) across 0.16–710 MHz, supports PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operates from 1.8/2.5/3.3 V core supply in a 4 × 4 mm 24-QFN package for FPGA, processor, and high-speed serial interface timing.

For engineers reviewing the SI5338N-B05174-GM datasheet, SI5338N-B05174-GM pinout, SI5338N-B05174-GM application, or SI5338N-B05174-GM equivalent, key selection criteria include its 0.7 ps RMS typical phase jitter, independent per-output voltage (1.5–3.3 V), programmable phase/frequency adjustment in 20 ps / 1 ppm steps, spread-spectrum capability (0.5–5.0% at 33–63 kHz), and support for multiple input references (crystal, CMOS, SSTL, differential up to 710 MHz).

Technical Context

The SI5338N-B05174-GM integrates a dual-stage PLL architecture: a high-stability reference PLL (Stage 1) locks to one of six input sources, followed by four independent MultiSynth™ fractional-N synthesizers (Stage 2) generating outputs with integer or fractional division. Each output driver supports format and voltage configuration independently, enabling mixed-signal clock trees without external level translation.

Its control architecture includes I²C/SMBus interface with OTP NVM storage, dedicated OEB/PINC/FDEC pins for real-time glitchless frequency/phase updates, loss-of-lock and loss-of-signal alarms, and external feedback mode for zero-delay operation. The device achieves <100 ps output-to-output skew and supports programmable initial phase offset from –45 ns to +45 ns.

Key Specifications

Pinout & Package

SI5338N-B05174-GM uses a 24-lead QFN package (4 × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin assignments are standardized across Si5338 variants per Skyworks documentation (Rev. 1.6, p. 37).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output programmable clock generator applications.

Compared with Si5332A-D05174-GM and ICS853S01AG-01, SI5338N-B05174-GM offers field-programmable frequency agility and per-output voltage/format control at the expense of higher power and external crystal dependency-making it optimal for mid-volume, design-flexible industrial and telecom platforms.

Availability

SI5338N-B05174-GM is available at Aetrix Electronics and suitable for PCIe Gen 4 root complexes, Ethernet switch/router timing, and broadcast video frame synchronization requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for SI5338N-B05174-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and mobile markets.

The Si5338 product line was designed to replace multiple discrete oscillators and buffers in high-speed digital systems, delivering programmable, low-jitter clock generation for PCIe, Ethernet, Fibre Channel, and broadcast video applications.

FAQ

What is the maximum differential input frequency supported by the SI5338N-B05174-GM?

The SI5338N-B05174-GM supports differential input frequencies up to 710 MHz on pins IN1/IN2 and IN5/IN6. This capability enables direct use of high-speed SerDes reference clocks (e.g., 622.08 MHz OC-12, 709.5 MHz 25G Ethernet) without external prescaling. Input slew rate must exceed 0.3 V/ns for optimal jitter performance, and external 100 Ω termination is required per differential pair.

Does the SI5338N-B05174-GM support PCIe Gen 4 Common Clock compliance?

Yes, the SI5338N-B05174-GM meets PCIe Gen 4 Common Clock jitter requirements with 0.15–0.45 ps RMS (12 kHz–20 MHz) when configured per Skyworks' recommended PLL bandwidth (2–4 MHz) and CDR settings. Validation was performed using the Skyworks PCIe Clock Jitter Tool and aligns with PCI-Express Base Specification 4.0 rev. 0.5. The device also supports Gen 1–3 Common Clock and Gen 3 SRNS modes.

Can the SI5338N-B05174-GM generate four different output frequencies simultaneously?

Yes, the SI5338N-B05174-GM synthesizes four independent output frequencies simultaneously using its four MultiSynth™ engines. Each output can be set to any frequency within its supported range (e.g., 100 MHz, 125 MHz, 156.25 MHz, 312.5 MHz), with zero ppm error and independent format/voltage configuration. Integer-mode operation ensures lowest jitter; fractional mode extends frequency resolution at minor jitter cost.

What is the purpose of the INTR pin on the SI5338N-B05174-GM?

The INTR pin on the SI5338N-B05174-GM is an open-drain interrupt output that asserts low during loss-of-lock (LOL) or loss-of-signal (LOS) conditions. It provides real-time fault detection without polling the I²C interface, enabling system-level monitoring and fail-safe responses. The pin is internally pulled up and compatible with 1.8/2.5/3.3 V logic; debouncing and edge-triggered interrupt handling are implemented in host firmware.

How is the SI5338N-B05174-GM programmed and configured?

The SI5338N-B05174-GM is programmed via its I²C/SMBus-compatible serial interface (SCL/SDA pins) using Skyworks' ClockBuilder Pro software, which auto-generates configuration files and register maps. Configuration is stored in on-chip OTP memory, enabling autonomous startup. Hardware pins (PINC/FDEC/OEB) allow runtime adjustments without I²C traffic, and the device supports both pin-strapped and I²C-addressed operation.