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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338N-B05315-GMR

Name: SI5338N-B05315-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338N-B05315-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338N-B05315-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338N-B05315-GMR.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5338N-B05315-GMR from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation across –40 to +85 °C in a 4 × 4 mm 24-QFN package. It replaces up to four crystal oscillators in high-speed serial interface timing applications.

For engineers reviewing the SI5338N-B05315-GMR datasheet, SI5338N-B05315-GMR pinout, SI5338N-B05315-GMR application, or SI5338N-B05315-GMR equivalent, key selection considerations include its MultiSynth™-based any-frequency synthesis (0.16–710 MHz per output), independent output voltage control (1.5/1.8/2.5/3.3 V), spread-spectrum capability (0.5–5.0% down-spread), and I²C/SMBus programmability with ClockBuilder Pro support.

Technical Context

The SI5338N-B05315-GMR implements a two-stage PLL architecture: a high-stability integer-N PLL (Stage 1) locks to one of six input references (crystal, CMOS, SSTL/HSTL, or differential), followed by four independent MultiSynth™ fractional-N synthesizers (Stage 2) generating each output. Each MultiSynth supports integer or fractional mode, enabling true zero-ppm frequency accuracy and <20 ps programmable phase steps.

Its output stage provides per-driver configurability for LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats, with independent VDDO supplies and internal 22 Ω series termination. The device supports glitchless frequency increment/decrement in 1 ppm steps via pin control or I²C, and includes loss-of-lock and loss-of-signal alarms with dedicated INTR pin.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps - meets PCIe Gen 3 SRNS and Gen 4 common clock jitter requirements at 100 MHz HCSL output
Output Frequency Range	0.16–710 MHz - covers PCIe (100/125 MHz), Ethernet (125/156.25 MHz), Fibre Channel (1.0625 GHz ÷ 2 = 531.25 MHz), and processor clocks
Input Reference Support	8–30 MHz crystal, 5–710 MHz differential, 5–350 MHz SSTL/HSTL - enables flexible system-level clock tree design
Supply Voltages	VDD = 1.8/2.5/3.3 V; VDDOx = 1.4–3.63 V - allows mixed-voltage board designs with independent output driver level setting
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch - space-efficient footprint compatible with standard PCB assembly processes
Operating Temperature	–40 to +85 °C - qualified for industrial and telecom line card environments
Spread Spectrum	0.5–5.0% down-spread, 33–63 kHz modulation - reduces EMI without requiring board-level filtering changes

Pinout & Package

SI5338N-B05315-GMR uses a 24-lead QFN package (4 × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin 1 is top-left corner (IN1), pin 24 is bottom-right (GND). Pin numbering follows standard counter-clockwise layout from top-left.

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2, IN5, IN6	Differential input pairs	Accept 5–710 MHz AC-coupled differential clocks; require external 100 Ω termination
IN3, IN4	Single-ended input pins	Support 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL; VIH/VIL referenced to VDD
CLK0A/CLK0B to CLK3A/CLK3B	Differential output pairs	Four independent outputs; each pair supports LVPECL/LVDS/HCSL/CML with per-driver VDDO
VDDO0–VDDO3	Output buffer supply pins	Enable independent voltage setting per output driver (1.5/1.8/2.5/3.3 V)
VDD	Core supply	1.8/2.5/3.3 V core power; PSRR optimized for clean clock generation
SCL, SDA	I²C interface	SMBus-compatible 100/400 kHz bus; supports ClockBuilder Pro configuration
INTR	Interrupt output	Open-drain status pin indicating loss-of-lock or loss-of-signal events

Key Features

Feature	Design Value
MultiSynth™ synthesis	Four independent fractional-N synthesizers enable simultaneous any-frequency outputs (e.g., 100 MHz PCIe + 125 MHz Ethernet + 156.25 MHz 10GbE + 200 MHz FPGA) with zero ppm error
PCIe Gen 3 SRNS compliance	0.11–0.32 ps RMS jitter in Separate Reference No Spread mode satisfies PCIe Base Spec 3.0 for root complex and endpoint timing
Independent phase adjustment	Programmable initial phase offset (–45 to +45 ns) and <20 ps step resolution per output - enables precise skew management in multi-lane SerDes systems
Glitchless frequency tuning	Pin-controlled frequency increment/decrement in 1 ppm steps with 667 ns update time (>18 MHz outputs) - supports dynamic rate adaptation without clock interruption
Flexible spread spectrum	Configurable on any output: 0.5–5.0% spread depth, 33–63 kHz modulation rate - reduces EMI peaks while preserving timing margin

Applications

PCIe Gen 4 Root Complex Timing	Ethernet Switch Clock Tree
Use Scenario: Providing synchronized 100 MHz common clock to CPU, GPU, and NVMe controllers in a server motherboard with PCIe Gen 4 x16 slots. IC Role / Device Role / Timing Role: Quad-output clock generator delivering low-jitter reference clocks with matched propagation delay and programmable phase alignment across all lanes. Use Value: Meets PCIe Gen 4 common clock TJ < 33.6 ps pk-pk requirement while eliminating four discrete XO placements and reducing BOM count.	Use Scenario: Generating 125 MHz (1 GbE), 156.25 MHz (10 GbE), 312.5 MHz (25 GbE), and 625 MHz (50 GbE) clocks for a multi-rate Ethernet switch ASIC. IC Role / Device Role / Timing Role: Any-frequency synthesizer with independent output format and voltage control per port (LVDS for 1 GbE, HCSL for 10/25 GbE). Use Value: Enables single-chip clock provisioning for heterogeneous Ethernet PHYs, avoiding multiple clock ICs and interposer routing complexity.
Broadcast Video Synchronization	FPGA-Based Test Equipment
Use Scenario: Delivering SMPTE ST 2059-2–compliant 27 MHz, 74.25 MHz, and 148.5 MHz reference clocks to video encoders, decoders, and genlock modules in broadcast infrastructure. IC Role / Device Role / Timing Role: Precision clock generator with sub-20 ps phase step resolution and zero-ppm synthesis accuracy for frame-accurate media synchronization. Use Value: Eliminates need for multiple TCXOs and analog phase shifters; supports real-time format switching via I²C reprogramming.	Use Scenario: Supplying 100 MHz system clock, 200 MHz ADC sampling clock, 300 MHz DAC reconstruction clock, and 400 MHz JESD204B link clock to a high-speed data acquisition FPGA platform. IC Role / Device Role / Timing Role: Configurable quad clock source with independent jitter-optimized outputs for mixed-signal subsystems. Use Value: Achieves <1 ps RMS jitter on critical sampling clocks while supporting dynamic reconfiguration during test sequence changes.

PCIe Gen 4 Root Complex Timing

Ethernet Switch Clock Tree

Use Scenario: Providing synchronized 100 MHz common clock to CPU, GPU, and NVMe controllers in a server motherboard with PCIe Gen 4 x16 slots.

IC Role / Device Role / Timing Role: Quad-output clock generator delivering low-jitter reference clocks with matched propagation delay and programmable phase alignment across all lanes.

Use Value: Meets PCIe Gen 4 common clock TJ < 33.6 ps pk-pk requirement while eliminating four discrete XO placements and reducing BOM count.

Use Scenario: Generating 125 MHz (1 GbE), 156.25 MHz (10 GbE), 312.5 MHz (25 GbE), and 625 MHz (50 GbE) clocks for a multi-rate Ethernet switch ASIC.

IC Role / Device Role / Timing Role: Any-frequency synthesizer with independent output format and voltage control per port (LVDS for 1 GbE, HCSL for 10/25 GbE).

Use Value: Enables single-chip clock provisioning for heterogeneous Ethernet PHYs, avoiding multiple clock ICs and interposer routing complexity.

Broadcast Video Synchronization

FPGA-Based Test Equipment

Use Scenario: Delivering SMPTE ST 2059-2–compliant 27 MHz, 74.25 MHz, and 148.5 MHz reference clocks to video encoders, decoders, and genlock modules in broadcast infrastructure.

IC Role / Device Role / Timing Role: Precision clock generator with sub-20 ps phase step resolution and zero-ppm synthesis accuracy for frame-accurate media synchronization.

Use Value: Eliminates need for multiple TCXOs and analog phase shifters; supports real-time format switching via I²C reprogramming.

Use Scenario: Supplying 100 MHz system clock, 200 MHz ADC sampling clock, 300 MHz DAC reconstruction clock, and 400 MHz JESD204B link clock to a high-speed data acquisition FPGA platform.

IC Role / Device Role / Timing Role: Configurable quad clock source with independent jitter-optimized outputs for mixed-signal subsystems.

Use Value: Achieves <1 ps RMS jitter on critical sampling clocks while supporting dynamic reconfiguration during test sequence changes.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D05315-GM	Higher integration: integrated crystal, smaller 3 × 3 mm 24-QFN, lower 0.35 ps RMS jitter, but fixed 4-output configuration with no pin-selectable variants	Targeted at space-constrained, ultra-low-jitter applications (e.g., optical modules); lacks Si5338's wide input flexibility (no 8–30 MHz crystal option)	Select when board area and jitter are primary constraints and crystal integration is acceptable
ICS853S01AGI-01LFT	Non-programmable, fixed-frequency 4-output LVDS clock generator; 0.9 ps RMS jitter; no I²C interface or spread spectrum	Used in cost-sensitive, static-clock applications (e.g., legacy storage controllers); requires separate clock buffers for voltage translation	Select only for fixed-frequency, non-reconfigurable designs where programmability is unnecessary

Compared with Si5332A-D05315-GM and ICS853S01AGI-01LFT, SI5338N-B05315-GMR uniquely balances field-programmability, wide input/output flexibility, and PCIe Gen 4 compliance in a mature, production-proven 4 × 4 mm QFN package-making it optimal for evolving high-speed serial interface platforms requiring post-silicon clock tuning.

Availability

SI5338N-B05315-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 server motherboards, multi-rate Ethernet switches, and broadcast video timing systems requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.

Supply support for SI5338N-B05315-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and power management ICs for wireless, broadband, automotive, and industrial markets.

The Si5338 family is designed as a programmable, low-jitter quad clock generator targeting high-speed serial interface timing-including PCIe, Ethernet, Fibre Channel, and broadcast video-where flexible frequency synthesis and robust jitter performance are critical.

FAQ

What is the maximum output frequency supported by SI5338N-B05315-GMR?

The SI5338N-B05315-GMR supports up to 710 MHz on LVPECL/LVDS/CML outputs, 350 MHz on SSTL/HSTL, 250 MHz on HCSL, and 200 MHz on CMOS. Frequencies above 350 MHz are limited to two unique values simultaneously (Fvco/4 and Fvco/6), as specified in the Si5338 datasheet Section 3.3. This capability enables direct support for PCIe Gen 4 (100 MHz), 10GbE (156.25 MHz), and 25GbE (312.5 MHz) reference clocks using the SI5338N-B05315-GMR.

Does SI5338N-B05315-GMR support PCIe Gen 4 Common Clock compliance?

Yes, SI5338N-B05315-GMR meets PCIe Gen 4 Common Clock jitter requirements with 0.15–0.45 ps RMS (10 kHz–50 MHz) when configured per AN562 guidelines using HCSL 100 MHz outputs and appropriate PLL bandwidth (2–4 or 2–5 MHz). Its measured jitter performance is validated with the Skyworks PCIe Clock Jitter Tool and aligns with PCI-Express Base Specification 4.0 rev. 0.5 - confirming SI5338N-B05315-GMR suitability for Gen 4 root complex and endpoint timing.

Can SI5338N-B05315-GMR generate different output voltages on each channel?

Yes, SI5338N-B05315-GMR provides independent VDDO0–VDDO3 pins allowing separate 1.5 V, 1.8 V, 2.5 V, or 3.3 V supply connections per output driver. This enables mixed-signal board designs where, for example, CLK0 drives a 1.8 V FPGA bank (LVDS), CLK1 feeds a 3.3 V microcontroller (CMOS), CLK2 clocks a 2.5 V Ethernet PHY (HCSL), and CLK3 serves a 1.5 V SerDes (LVPECL) - all from a single SI5338N-B05315-GMR device.

How is SI5338N-B05315-GMR programmed and configured?

SI5338N-B05315-GMR is programmed via its I²C/SMBus-compatible interface (SCL/SDA pins) using Skyworks' ClockBuilder Pro software, which auto-generates register maps and configuration files based on user-defined frequency, format, and voltage requirements. Configuration can be stored in on-chip OTP NVM for power-on initialization, or dynamically updated in-system - enabling full SI5338N-B05315-GMR reprogramming without hardware changes.

What package type and thermal characteristics does SI5338N-B05315-GMR have?

SI5338N-B05315-GMR uses a 24-lead QFN package measuring 4 × 4 mm with 0.5 mm pitch and an exposed thermal pad. Its thermal resistance is θJA = 37 °C/W (still air) and θJC = 10 °C/W, enabling reliable operation at full load (45 mA core current) across –40 to +85 °C ambient. The package is RoHS-compliant and compatible with standard reflow profiles per JEDEC J-STD-020 - ensuring manufacturability in SI5338N-B05315-GMR-based designs.

SI5338N-B05315-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338N-B05315-GMR FAQ

1.How can I place an order for SI5338N-B05315-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338N-B05315-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338N-B05315-GMR reliable?

The price and inventory of SI5338N-B05315-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338N-B05315-GMR is usually 5 days.

3.What payment methods are accepted for SI5338N-B05315-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338N-B05315-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338N-B05315-GMR?

SI5338N-B05315-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338N-B05315-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338N-B05315-GMR?

For technical support, including SI5338N-B05315-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338N-B05315-GMR requirements.

6.How does Aetrix verify that SI5338N-B05315-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338N-B05315-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338N-B05315-GMR meets industry standards.

7.What is the process for return or replacement of SI5338N-B05315-GMR?

All SI5338N-B05315-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338N-B05315-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338N-B05315-GMR part is unused and in its original packaging.

Return procedure for SI5338N-B05315-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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