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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338N-B05635-GMR

Name: SI5338N-B05635-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338N-B05635-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338N-B05635-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338N-B05635-GMR.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5338N-B05635-GMR from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 and SRNS compliance, and MultiSynth™ frequency synthesis supporting 0.16–710 MHz output ranges across LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats. It replaces up to four crystal oscillators in high-speed serial interface timing applications.

For engineers reviewing the SI5338N-B05635-GMR datasheet, SI5338N-B05635-GMR pinout, SI5338N-B05635-GMR application, or SI5338N-B05635-GMR equivalent, key selection criteria include PCIe Gen 4 common-clock jitter (0.15–0.45 ps RMS), independent per-output voltage (1.5/1.8/2.5/3.3 V), 24-pin 4×4 mm QFN package, and I²C/SMBus programmability with ClockBuilder Pro support.

Technical Context

The SI5338N-B05635-GMR implements a two-stage PLL architecture: a high-stability reference stage followed by four independent MultiSynth™ fractional-N synthesizers, each driving one output pair. Input flexibility includes external crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), or differential (5–710 MHz) references.

Each output supports independent format selection, voltage rail assignment (VDDO0–VDDO3), phase offset (<20 ps steps), frequency increment/decrement (1 ppm steps), and spread-spectrum control (0.5–5.0% spread, 33–63 kHz modulation). Loss-of-lock and loss-of-signal alarms provide real-time status monitoring via INTR pin.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps - meets PCIe Gen 4 common-clock jitter requirement (≤0.45 ps RMS) under specified test conditions
Output Frequency Range	0.16–710 MHz - covers PCIe 100 MHz, Ethernet 125/156.25 MHz, Fibre Channel 1.0625 GHz (via /2 divider), and processor clocks
Input Reference Support	8–30 MHz crystal, 5–710 MHz differential - enables direct replacement of multiple XO sources with one flexible input
Output Driver Flexibility	LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL - allows mixed-signal board-level clock distribution without level-shifting ICs
Supply Voltages	VDD = 1.8/2.5/3.3 V; VDDOx = 1.5/1.8/2.5/3.3 V - supports heterogeneous SoC/FPGA I/O voltage domains
Package	24-pin QFN, 4 × 4 mm - space-constrained designs requiring four precision clocks in minimal footprint
Operating Temperature	–40 to +85 °C - qualified for industrial and telecom line-card environments

Pinout & Package

SI5338N-B05635-GMR uses a 24-lead, 4 × 4 mm QFN package with exposed thermal pad. Pin assignments are fixed per Si5338 family: six input pins (IN1–IN6), eight clock output pins (CLK0A/B through CLK3A/B), four VDDO supply pins (VDDO0–VDDO3), dual VDD core supplies, SCL/SDA/I²C interface, INTR alarm output, and reserved ground.

Pin/Terminal	Circuit Role	Design Meaning
IN1/IN2, IN5/IN6	Differential reference inputs	Accept 5–710 MHz AC-coupled differential clocks; require external 100 Ω termination
IN3/IN4	Single-ended reference inputs	Support 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL with internal biasing
CLK0A/CLK0B – CLK3A/CLK3B	Differential clock outputs	Four independent pairs; each configurable as LVPECL/LVDS/HCSL/CML with dedicated VDDO rail
VDDO0–VDDO3	Output buffer supply rails	Enable per-output voltage setting (1.5/1.8/2.5/3.3 V) to match connected device I/O standards
SCL/SDA	I²C/SMBus interface	Standard 2-wire bus for configuration; supports ClockBuilder Pro programming and runtime reconfiguration
INTR	Interrupt output	Open-drain status pin asserting on loss-of-lock or loss-of-signal events

Key Features

Feature	Design Value
Independent per-output phase adjustment	±45 ns range in <20 ps steps - enables precise skew compensation across multi-lane SerDes interfaces
Glitchless frequency tuning	1 ppm step size with pin-controlled increment/decrement - allows dynamic clock rate adaptation without output interruption
PCIe Gen 3 SRNS compliance	0.11–0.32 ps RMS jitter in separate-reference mode - satisfies strict jitter budget for Gen 3 root complex and endpoint timing
Configurable spread spectrum	0.5–5.0% spread at 33–63 kHz - reduces EMI peak emissions for FCC/CE certification without affecting system timing margins
External feedback mode	Enables zero-delay operation - eliminates propagation delay between input reference and output clocks for synchronous buffering

Applications

PCIe Gen 4 Switch Timing	Ethernet 10GbE PHY Clocking
Use Scenario: Providing synchronized 100 MHz common reference clocks to PCIe Gen 4 switch ASICs and attached endpoints in server backplanes. IC Role / Device Role / Timing Role: Quad-output clock generator delivering low-jitter, phase-aligned clocks meeting PCIe Gen 4 common-clock jitter spec (0.15–0.45 ps RMS). Use Value: Eliminates need for four discrete XOs; enables single-point configuration and dynamic frequency margining during validation.	Use Scenario: Generating 156.25 MHz and 312.5 MHz clocks for 10GbE PHYs and MACs in telecom line cards and enterprise switches. IC Role / Device Role / Timing Role: Any-frequency synthesizer producing exact IEEE 802.3ae-compliant frequencies with <1 ps RMS jitter. Use Value: Supports both base-R and WAN-PHY modes from one device; avoids external dividers or multiplexers.
Broadcast Video Frame Sync	FPGA-Based Video Processing
Use Scenario: Delivering genlock-capable 27 MHz, 74.25 MHz, and 148.5 MHz pixel clocks to SDI transmitters, receivers, and frame synchronizers in broadcast infrastructure. IC Role / Device Role / Timing Role: High-precision clock generator with programmable initial phase offset (±45 ns) and sub-20 ps phase step resolution. Use Value: Enables deterministic inter-device phase alignment across multi-channel video pipelines without manual delay tuning.	Use Scenario: Supplying multiple independent clocks (e.g., 100 MHz system, 250 MHz transceiver, 500 MHz DDR) to Xilinx Versal or Intel Agilex FPGAs in real-time video analytics systems. IC Role / Device Role / Timing Role: Configurable quad clock source with per-output voltage (1.8/2.5/3.3 V) and format (LVDS/HCSL/CMOS) matching FPGA bank requirements. Use Value: Reduces BOM count and PCB routing complexity versus discrete clock trees; supports dynamic reconfiguration via I²C during mode switching.

PCIe Gen 4 Switch Timing

Ethernet 10GbE PHY Clocking

Use Scenario: Providing synchronized 100 MHz common reference clocks to PCIe Gen 4 switch ASICs and attached endpoints in server backplanes.

IC Role / Device Role / Timing Role: Quad-output clock generator delivering low-jitter, phase-aligned clocks meeting PCIe Gen 4 common-clock jitter spec (0.15–0.45 ps RMS).

Use Value: Eliminates need for four discrete XOs; enables single-point configuration and dynamic frequency margining during validation.

Use Scenario: Generating 156.25 MHz and 312.5 MHz clocks for 10GbE PHYs and MACs in telecom line cards and enterprise switches.

IC Role / Device Role / Timing Role: Any-frequency synthesizer producing exact IEEE 802.3ae-compliant frequencies with <1 ps RMS jitter.

Use Value: Supports both base-R and WAN-PHY modes from one device; avoids external dividers or multiplexers.

Broadcast Video Frame Sync

FPGA-Based Video Processing

Use Scenario: Delivering genlock-capable 27 MHz, 74.25 MHz, and 148.5 MHz pixel clocks to SDI transmitters, receivers, and frame synchronizers in broadcast infrastructure.

IC Role / Device Role / Timing Role: High-precision clock generator with programmable initial phase offset (±45 ns) and sub-20 ps phase step resolution.

Use Value: Enables deterministic inter-device phase alignment across multi-channel video pipelines without manual delay tuning.

Use Scenario: Supplying multiple independent clocks (e.g., 100 MHz system, 250 MHz transceiver, 500 MHz DDR) to Xilinx Versal or Intel Agilex FPGAs in real-time video analytics systems.

IC Role / Device Role / Timing Role: Configurable quad clock source with per-output voltage (1.8/2.5/3.3 V) and format (LVDS/HCSL/CMOS) matching FPGA bank requirements.

Use Value: Reduces BOM count and PCB routing complexity versus discrete clock trees; supports dynamic reconfiguration via I²C during mode switching.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D05635-GM	Higher integration: integrated crystal, lower jitter (0.35 ps RMS), supports up to 10 outputs, but larger 32-QFN package	Better suited for new designs requiring ultra-low jitter and crystal-free layout; not drop-in compatible due to pin count and footprint change	Select when PCIe Gen 5 readiness, reduced bill-of-materials, or tighter jitter budgets are required; verify PCB redesign feasibility.
ICS853S01AGI-01LFT	Fixed-frequency, non-programmable quad LVDS generator; 1.2 ps RMS jitter; 3.3 V only; no I²C interface	Limited to static clock trees where frequencies never change; lacks spread spectrum, phase control, or voltage flexibility	Choose only for cost-sensitive, high-volume applications with unchanging clock requirements and no need for field updates or margining.

Compared with Si5332A-D05635-GM and ICS853S01AGI-01LFT, SI5338N-B05635-GMR offers optimal balance of programmability, jitter performance, and pin-compatible upgrade path within the Si5338 family-enabling firmware-based clock tree optimization without hardware changes.

Availability

SI5338N-B05635-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, 10GbE PHY clocking, and broadcast video frame sync applications requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for SI5338N-B05635-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5338 product line delivers programmable, low-jitter clock generation for high-speed serial interfaces-including PCIe, Ethernet, Fibre Channel, and broadcast video-where precise frequency synthesis and deterministic phase control are critical.

FAQ

What is the primary function of the SI5338N-B05635-GMR in a PCIe Gen 4 system?

The SI5338N-B05635-GMR serves as a quad-output common-reference clock generator delivering four synchronized 100 MHz clocks with ≤0.45 ps RMS jitter to meet PCIe Gen 4 common-clock specifications. Its MultiSynth™ architecture ensures zero-ppm frequency accuracy and independent phase alignment across all outputs, enabling reliable link training and stable data transfer in switch and endpoint applications.

Does the SI5338N-B05635-GMR support spread-spectrum clocking (SSC), and what are its configurable parameters?

Yes, the SI5338N-B05635-GMR supports fully configurable spread-spectrum clocking on any output: spread percentage adjustable from 0.5% to 5.0%, modulation rate from 33 kHz to 63 kHz, and selectable down-spread or center-spread profiles. These settings are programmed via I²C registers and validated per JEDEC and PCI-SIG EMI reduction guidelines without compromising timing integrity.

How does the SI5338N-B05635-GMR handle different output voltage requirements for mixed-signal FPGA designs?

The SI5338N-B05635-GMR provides four independent VDDO supply pins (VDDO0–VDDO3), each configurable for 1.5 V, 1.8 V, 2.5 V, or 3.3 V operation. This allows each of its four output drivers to drive interfaces with differing I/O standards-such as 1.8 V LVDS for transceivers and 3.3 V CMOS for control logic-without external level shifters or discrete regulators.

Can the SI5338N-B05635-GMR operate in clock buffer (PLL bypass) mode, and what is its additive jitter in that mode?

Yes, the SI5338N-B05635-GMR supports clock buffer mode with PLL bypass, achieving 0.165 ps RMS additive phase jitter (12 kHz–20 MHz) using a 622.08 MHz differential input. This mode preserves input clock integrity while distributing it to multiple loads with minimal degradation-ideal for low-latency, zero-delay fanout applications where synthesis is unnecessary.

What development tools are officially supported for configuring the SI5338N-B05635-GMR?

Skyworks' ClockBuilder Pro software is the official GUI tool for configuring the SI5338N-B05635-GMR, enabling full register setup, frequency planning, jitter simulation, and I²C script generation. The PCIe Clock Jitter Tool is also provided for automated compliance testing against PCIe Gen 1–4 jitter masks using standard oscilloscope measurements.

SI5338N-B05635-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338N-B05635-GMR FAQ

1.How can I place an order for SI5338N-B05635-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338N-B05635-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338N-B05635-GMR reliable?

The price and inventory of SI5338N-B05635-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338N-B05635-GMR is usually 5 days.

3.What payment methods are accepted for SI5338N-B05635-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338N-B05635-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338N-B05635-GMR?

SI5338N-B05635-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338N-B05635-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338N-B05635-GMR?

For technical support, including SI5338N-B05635-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338N-B05635-GMR requirements.

6.How does Aetrix verify that SI5338N-B05635-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338N-B05635-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338N-B05635-GMR meets industry standards.

7.What is the process for return or replacement of SI5338N-B05635-GMR?

All SI5338N-B05635-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338N-B05635-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338N-B05635-GMR part is unused and in its original packaging.

Return procedure for SI5338N-B05635-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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