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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338N-B05866-GM

Name: SI5338N-B05866-GM
Brand: Skyworks Solutions Inc.
SKU: SI5338N-B05866-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338N-B05866-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338N-B05866-GM.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5338N-B05866-GM from Skyworks Solutions is a quad-output, I²C-programmable clock generator with MultiSynth™ frequency synthesis, delivering four independent low-jitter clocks (0.7 ps RMS typ) across LVPECL/LVDS/HCSL/CMOS/SSTL formats, supporting PCIe Gen 1–4 and Ethernet timing in telecom line cards and FPGA clocking.

For engineers reviewing the SI5338N-B05866-GM datasheet, SI5338N-B05866-GM pinout, SI5338N-B05866-GM application, or SI5338N-B05866-GM equivalent, key selection considerations include its 4× differential output capability, 0 ppm synthesis accuracy, 24-QFN package, PCIe Gen 4 SRNS compliance, and I²C-based configuration via ClockBuilder Pro software.

Technical Context

The SI5338N-B05866-GM implements a two-stage PLL architecture: a high-stability reference stage followed by four independent MultiSynth™ fractional-N synthesizers, each driving a configurable output buffer. It supports external crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), or differential (5–710 MHz) inputs.

Each output driver supports independent voltage (1.5/1.8/2.5/3.3 V), format (LVPECL up to 710 MHz, HCSL up to 250 MHz, CMOS up to 200 MHz), phase offset (<20 ps steps), and spread-spectrum control (0.5–5.0% spread, 33–63 kHz modulation). Loss-of-lock and loss-of-signal alarms are integrated.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase jitter (RMS)	0.7 ps typical - meets PCIe Gen 4 common clock and SRNS requirements at 100 MHz HCSL output.
Output count & type	4 differential outputs (CLK0A/B, CLK1A/B, CLK2A/B, CLK3A/B) - supports simultaneous LVPECL, LVDS, HCSL, or CML signaling.
Frequency range	0.16–710 MHz per output - covers 1 GbE (125 MHz), 10 GbE (156.25 MHz), PCIe Gen 4 (100 MHz), and Fibre Channel (212.5/266.6 MHz).
Input flexibility	8–30 MHz crystal, 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL, or 5–710 MHz differential - enables single-device replacement of multiple XO/VCXO sources.
Supply & temp	1.8/2.5/3.3 V core supply; –40 to +85 °C operation - suitable for industrial and telecom environments without derating.
Package	24-pin QFN, 4 × 4 mm - compact footprint compatible with high-density FPGA/ASIC timing layouts.

Pinout & Package

SI5338N-B05866-GM uses a 24-lead, 4 × 4 mm QFN package with exposed thermal pad. Pin assignments follow the Si5338 family layout: dual differential inputs (IN1/IN2, IN5/IN6), single-ended inputs (IN3, IN4), four differential output pairs (CLK0A/B through CLK3A/B), three VDDO supplies (VDDO0–VDDO3), shared VDD and GND, I²C interface (SCL/SDA), interrupt (INTR), and reserved ground (RSVD_GND).

Pin/Terminal	Circuit Role	Design Meaning
CLK0A / CLK0B	Differential output pair 0	Configurable as LVPECL/LVDS/HCSL/CML; independently set frequency, format, voltage, and phase.
CLK1A / CLK1B	Differential output pair 1	Same configurability as CLK0; supports integer/fractional synthesis with <20 ps phase step resolution.
CLK2A / CLK2B	Differential output pair 2	Supports frequencies up to 710 MHz (LVPECL) or 350 MHz (LVDS); enables multi-rate clocking for SerDes lanes.
CLK3A / CLK3B	Differential output pair 3	Independent SSC enable; used for EMI reduction on noise-sensitive subsystems like ADC/DAC clocks.
IN1 / IN2, IN5 / IN6	Differential reference inputs	Accept 5–710 MHz AC-coupled signals; internal 100 Ω termination; optimized for low-additive jitter.
IN3 / IN4	Single-ended reference inputs	Support CMOS/SSTL/HSTL; 5–350 MHz range; slew rate >1 V/ns recommended for jitter performance.
VDDO0–VDDO3	Output buffer supplies	Independent 1.4–3.63 V rails per output bank - allows mixed-voltage system interfacing (e.g., 1.8 V FPGA + 3.3 V PHY).
SCL / SDA	I²C/SMBus interface	Standard 100/400 kHz operation; supports in-system programming and real-time frequency adjustment.
INTR	Interrupt output	Open-drain status flag for loss-of-lock or loss-of-signal events; enables autonomous system fault response.

Key Features

Feature	Design Value
MultiSynth™ synthesis	Four independent fractional-N synthesizers deliver true zero-ppm accuracy on all outputs - eliminates need for trimming or calibration.
PCIe Gen 4 SRNS compliance	0.11–0.32 ps RMS jitter in Separate Reference No Spread mode - satisfies Intel's stringent jitter budget for Gen 4 root complex and endpoint timing.
Glitchless frequency tuning	1 ppm incremental/decremental adjustment via PINC/FDEC pins - enables dynamic clock scaling without output interruption.
Programmable phase offset	±45 ns range with <20 ps step resolution - supports precise skew alignment across multi-lane interfaces (e.g., DDR, JESD204B).
Flexible spread spectrum	Configurable 0.5–5.0% down-spread at 33–63 kHz - reduces EMI peak amplitude while maintaining timing integrity for FCC/CE certification.

Applications

Processor and FPGA clocking	PCIe Gen 1/2/3/4
Use Scenario: Providing synchronized clocks to multi-core processors and Xilinx/Intel FPGAs with mixed I/O standards and voltage domains. IC Role / Device Role / Timing Role: Quad-output programmable clock generator delivering independent 100 MHz, 125 MHz, 156.25 MHz, and 312.5 MHz clocks with sub-1 ps jitter. Use Value: Eliminates four discrete oscillators; supports dynamic reconfiguration via I²C during boot or runtime for power-aware clock gating.	Use Scenario: Generating compliant reference clocks for PCIe root complexes, switches, and endpoints across Gen 1–4. IC Role / Device Role / Timing Role: Common clock source meeting PCIe Gen 4 SRNS jitter spec (0.11–0.32 ps RMS) with 100 MHz HCSL output. Use Value: Single-chip solution replaces legacy clock trees; enables board-level jitter optimization via ClockBuilder Pro tuning.
Ethernet switch/router	Broadcast video/audio timing
Use Scenario: Timing 1 GbE and 10 GbE PHYs, packet processors, and traffic managers in carrier-grade switches. IC Role / Device Role / Timing Role: Four-output generator supplying 125 MHz (GbE), 156.25 MHz (10GbE), 312.5 MHz (25GbE), and 625 MHz (50GbE) clocks with matched skew. Use Value: Reduces BOM count and layout complexity; supports IEEE 1588 PTP synchronization via precise phase control.	Use Scenario: Synchronizing SDI, HDMI, and AES audio clocks in broadcast encoders, routers, and IP media gateways. IC Role / Device Role / Timing Role: Low-jitter source for SMPTE ST 2082 (12G-SDI), AES67 (48/96 kHz), and HDMI 2.1 (324 MHz) reference clocks. Use Value: Meets ±20 ppm genlock stability; enables frame-accurate switching between video sources using programmable phase offsets.

Processor and FPGA clocking

PCIe Gen 1/2/3/4

Use Scenario: Providing synchronized clocks to multi-core processors and Xilinx/Intel FPGAs with mixed I/O standards and voltage domains.

IC Role / Device Role / Timing Role: Quad-output programmable clock generator delivering independent 100 MHz, 125 MHz, 156.25 MHz, and 312.5 MHz clocks with sub-1 ps jitter.

Use Value: Eliminates four discrete oscillators; supports dynamic reconfiguration via I²C during boot or runtime for power-aware clock gating.

Use Scenario: Generating compliant reference clocks for PCIe root complexes, switches, and endpoints across Gen 1–4.

IC Role / Device Role / Timing Role: Common clock source meeting PCIe Gen 4 SRNS jitter spec (0.11–0.32 ps RMS) with 100 MHz HCSL output.

Use Value: Single-chip solution replaces legacy clock trees; enables board-level jitter optimization via ClockBuilder Pro tuning.

Ethernet switch/router

Broadcast video/audio timing

Use Scenario: Timing 1 GbE and 10 GbE PHYs, packet processors, and traffic managers in carrier-grade switches.

IC Role / Device Role / Timing Role: Four-output generator supplying 125 MHz (GbE), 156.25 MHz (10GbE), 312.5 MHz (25GbE), and 625 MHz (50GbE) clocks with matched skew.

Use Value: Reduces BOM count and layout complexity; supports IEEE 1588 PTP synchronization via precise phase control.

Use Scenario: Synchronizing SDI, HDMI, and AES audio clocks in broadcast encoders, routers, and IP media gateways.

IC Role / Device Role / Timing Role: Low-jitter source for SMPTE ST 2082 (12G-SDI), AES67 (48/96 kHz), and HDMI 2.1 (324 MHz) reference clocks.

Use Value: Meets ±20 ppm genlock stability; enables frame-accurate switching between video sources using programmable phase offsets.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D05866-GM	Higher integration: includes integrated crystal, lower power (32 mA typ), enhanced jitter (0.45 ps RMS), but limited to 3 outputs.	Preferred for space-constrained designs where crystal integration and ultra-low jitter outweigh 4-output requirement.	Select when board area and jitter margin are critical, and 3 outputs suffice for system clock tree.
ICS853S01AG-01	Fixed-frequency, non-programmable; 4 LVDS outputs; 0.9 ps RMS jitter; no I²C interface or spread spectrum.	Suitable only for static clocking needs with no frequency agility or EMI control requirements.	Choose only if design uses fixed frequencies and avoids firmware-based configuration entirely.

Compared with Si5332A-D05866-GM and ICS853S01AG-01, the SI5338N-B05866-GM uniquely balances full I²C programmability, four independent outputs, PCIe Gen 4 SRNS compliance, and flexible input support - making it optimal for reconfigurable, multi-standard timing systems requiring field-upgradable clocking.

Availability

SI5338N-B05866-GM is available at Aetrix Electronics and suitable for telecom line cards, FPGA-based test equipment, and 10 GbE switch/router designs requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for SI5338N-B05866-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and mobile markets.

The Si5338 product line delivers highly configurable, low-jitter clock generation for high-speed serial interfaces including PCIe, Ethernet, and Fibre Channel - designed to replace multiple discrete oscillators with a single programmable IC.

FAQ

What is the maximum output frequency supported by SI5338N-B05866-GM in LVPECL format?

The SI5338N-B05866-GM supports up to 710 MHz in LVPECL format per output channel. This capability enables direct clocking of high-speed SerDes lanes in 25G/50G Ethernet and CPRI/eCPRI applications. Operation above 350 MHz requires use of Fvco/4 or Fvco/6 synthesis paths, limiting simultaneous high-frequency outputs to two unique frequencies.

Does SI5338N-B05866-GM support PCIe Gen 4 Separate Reference No Spread (SRNS) mode?

Yes, SI5338N-B05866-GM is explicitly validated for PCIe Gen 4 SRNS mode with 0.11–0.32 ps RMS jitter at 100 MHz HCSL output under specified PLL bandwidth (2–4 or 2–5 MHz) and CDR (10 MHz) conditions. This compliance is documented in Table 12 of the official Skyworks datasheet Rev. 1.6.

How many independent supply voltages can be applied to the output buffers of SI5338N-B05866-GM?

SI5338N-B05866-GM supports four independent output buffer supply rails: VDDO0, VDDO1, VDDO2, and VDDO3. Each can be set to 1.5 V, 1.8 V, 2.5 V, or 3.3 V, enabling mixed-voltage clock distribution to diverse devices such as 1.8 V FPGAs, 2.5 V PHYs, and 3.3 V legacy controllers on the same board.

Can SI5338N-B05866-GM generate spread-spectrum clocking on individual outputs?

Yes, SI5338N-B05866-GM provides per-output spread-spectrum control with user-selectable parameters: spread magnitude (0.5–5.0%), modulation rate (33–63 kHz), and direction (down-spread only). This feature is configurable independently for any enabled output, allowing targeted EMI reduction without affecting other clock domains.

What development tools are officially supported for configuring SI5338N-B05866-GM?

Skyworks' ClockBuilder Pro software is the officially supported configuration tool for SI5338N-B05866-GM. It provides GUI-based frequency planning, jitter analysis, register mapping, and .c file generation for embedded initialization. The SI5338N-B05866-GM is preloaded in the device library, and configuration files can be programmed via I²C or stored in on-chip OTP memory.

SI5338N-B05866-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tray

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338N-B05866-GM FAQ

1.How can I place an order for SI5338N-B05866-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338N-B05866-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338N-B05866-GM reliable?

The price and inventory of SI5338N-B05866-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338N-B05866-GM is usually 5 days.

3.What payment methods are accepted for SI5338N-B05866-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338N-B05866-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338N-B05866-GM?

SI5338N-B05866-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338N-B05866-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338N-B05866-GM?

For technical support, including SI5338N-B05866-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338N-B05866-GM requirements.

6.How does Aetrix verify that SI5338N-B05866-GM is sourced from the original manufacturer or authorized distributors?

All SI5338N-B05866-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338N-B05866-GM meets industry standards.

7.What is the process for return or replacement of SI5338N-B05866-GM?

All SI5338N-B05866-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338N-B05866-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338N-B05866-GM part is unused and in its original packaging.

Return procedure for SI5338N-B05866-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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