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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338N-B05866-GMR

Name: SI5338N-B05866-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338N-B05866-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338N-B05866-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338N-B05866-GMR.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5338N-B05866-GMR from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 and SRNS compliance, and support for any-frequency synthesis from 0.16 MHz to 710 MHz across LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats. It replaces up to four crystal oscillators in high-speed serial interface timing applications.

For engineers reviewing the SI5338N-B05866-GMR datasheet, SI5338N-B05866-GMR pinout, SI5338N-B05866-GMR application, or SI5338N-B05866-GMR equivalent, key selection criteria include PCIe Gen 4 common-clock jitter (0.15–0.45 ps RMS), independent per-output voltage control (1.5/1.8/2.5/3.3 V), MultiSynth™ fractional-N synthesis resolution (1 ppb), spread-spectrum capability (0.5–5.0% down-spread), and 4×4 mm 24-QFN package compatibility with industrial temperature range (–40 to +85 °C).

Technical Context

The SI5338N-B05866-GMR implements a two-stage PLL architecture: a high-stability integer-N Phase-Locked Loop (Stage 1) locks to one of six input references (crystal, CMOS, SSTL/HSTL, or differential), followed by four independent MultiSynth™ fractional-N synthesis blocks (Stage 2) generating output clocks with true zero-ppm accuracy. Each output driver supports programmable format, voltage, slew rate, and termination.

It features dedicated loss-of-lock and loss-of-signal alarms, independent phase/frequency increment/decrement control (20 ps / 1 ppm steps), external feedback mode for zero-delay operation, and I²C/SMBus-compatible configuration via 24-bit address space. The device operates from a single 1.8/2.5/3.3 V core supply with 45 mA typical current draw and integrates OTP NVM for factory or field programming.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps - meets PCIe Gen 4 common-clock jitter spec (≤0.45 ps RMS) under defined test conditions
Output Frequency Range	0.16–710 MHz - covers PCIe 100 MHz, Ethernet 125/156.25 MHz, Fibre Channel 1.0625 GHz (via /2 divider), and processor/FPGA clock domains
Synthesis Resolution	1 ppb - enables exact frequency matching (e.g., 156.250000 MHz) without rounding error in integer or fractional mode
Input Reference Support	8–30 MHz crystal, 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL, 5–710 MHz differential - eliminates need for external buffer or level translator
Supply Voltage	Core: 1.8/2.5/3.3 V ±10%; Output buffers: 1.4–3.63 V - allows mixed-voltage system integration with independent VDDO per output bank
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch - compatible with standard PCB assembly and thermal management for industrial ambient (–40 to +85 °C)
PCIe Compliance	Gen 1/2/3/4 Common Clock & Gen 3 SRNS - validated per Intel Clock Jitter Tool v1.6.4 using HCSL 100 MHz outputs

Pinout & Package

The SI5338N-B05866-GMR is housed in a thermally enhanced 24-lead QFN package (4 mm × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin 1 is top-left corner (IN1), pin 24 is bottom-right (GND). Package conforms to JEDEC MO-220, RoHS-compliant, MSL3.

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2, IN5, IN6	Differential input pairs	Accept 5–710 MHz AC-coupled differential clocks; require external 100 Ω termination; support low-jitter reference injection
IN3, IN4	Single-ended inputs	Accept 5–200 MHz CMOS-level clocks; VIH = 0.7×VDD, VIL = 0.3×VDD; internal 20 kΩ pull-up/pull-down configurable
CLK0A/CLK0B – CLK3A/CLK3B	Differential output pairs	Four independent LVPECL/LVDS/HCSL/CML outputs; each pair supports separate format, voltage (VDDO0–VDDO3), and enable control
VDDO0–VDDO3	Output buffer supplies	Independent 1.4–3.63 V rails per output bank - enables mixed-signal timing (e.g., 1.8 V FPGA + 3.3 V legacy PHY)
VDD	Core supply	Single 1.8/2.5/3.3 V supply powers PLL, synthesizers, and logic; PSRR >60 dB reduces power-supply noise coupling
SCL, SDA	I²C interface	Standard SMBus-compatible 2-wire bus (up to 400 kHz); supports multi-drop configuration with hardware address pins
INTR	Interrupt output	Open-drain status flag indicating loss-of-lock, loss-of-signal, or register write completion; active-low, 3 mA sink capability
RSVD_GND	Reserved ground	Internal no-connect; must be tied to GND for mechanical stability and EMI control per layout guidelines

Key Features

Feature	Design Value
MultiSynth™ Any-Frequency Synthesis	Four independent output clocks synthesized from same reference with 1 ppb resolution - eliminates multiple XO BOMs and board space
PCIe Gen 4 Common Clock Compliance	0.15–0.45 ps RMS jitter at 100 MHz HCSL output - meets PCIe Base Spec 4.0 rev 0.5 for host/root complex timing
Independent Per-Output Voltage Control	VDDO0–VDDO3 configurable from 1.5 V to 3.3 V - supports heterogeneous SoC/FPGA interfaces without level shifters
Programmable Spread Spectrum	0.5–5.0% down-spread at 33–63 kHz modulation - reduces EMI peak amplitude by >10 dB without affecting system timing margin
Glitchless Frequency Adjustment	1 ppm step size with <667 ns update time - enables dynamic clock scaling in real-time systems without output interruption
External Feedback Mode	Zero-delay operation via fb pin - synchronizes output phase to external clock source for deterministic latency in daisy-chain topologies

Applications

PCIe Gen 4 Switch Timing	Ethernet 10GbE/25GbE PHY Clocking
Use Scenario: Providing synchronized 100 MHz common clock to PCIe Gen 4 switch fabric with strict jitter budget (≤0.45 ps RMS). IC Role / Device Role / Timing Role: Primary clock generator delivering four identical, low-jitter HCSL outputs to switch ASIC and attached endpoints. Use Value: Meets PCIe Gen 4 common-clock jitter spec without external jitter cleaners; eliminates need for four discrete XOs and reduces layout complexity.	Use Scenario: Generating 156.25 MHz and 312.5 MHz clocks for 10GbE KR and 25GbE KR PHYs in telecom line cards. IC Role / Device Role / Timing Role: Dual-frequency, dual-format clock source with independent LVDS and CML outputs driving backplane and chip-to-chip links. Use Value: Single-device solution replaces two oscillators and one buffer; supports both IEEE 802.3bj and 802.3by timing requirements with shared reference stability.
Broadcast Video Frame Sync	FPGA-Based Video Processing
Use Scenario: Delivering genlock-capable 27 MHz, 74.25 MHz, and 148.5 MHz clocks to SDI transmitters, receivers, and frame synchronizers in broadcast infrastructure. IC Role / Device Role / Timing Role: Multi-format clock synthesizer with sub-ns phase alignment across outputs for SMPTE ST 2081-10 compliance. Use Value: Achieves <100 ps inter-output skew and programmable initial phase offset (±45 ns) - enables precise video pipeline synchronization without external delay lines.	Use Scenario: Supplying 50 MHz system clock, 200 MHz DDR3 interface clock, and 300 MHz video processing clock to Xilinx Zynq Ultrascale+ MPSoC. IC Role / Device Role / Timing Role: Configurable clock hub with CMOS, LVDS, and SSTL outputs matched to FPGA I/O standards and voltage domains. Use Value: Eliminates three discrete clock sources; supports simultaneous 1.8 V (FPGA core), 2.5 V (DDR3), and 3.3 V (legacy peripherals) supply rails via independent VDDO banks.

PCIe Gen 4 Switch Timing

Ethernet 10GbE/25GbE PHY Clocking

Use Scenario: Providing synchronized 100 MHz common clock to PCIe Gen 4 switch fabric with strict jitter budget (≤0.45 ps RMS).

IC Role / Device Role / Timing Role: Primary clock generator delivering four identical, low-jitter HCSL outputs to switch ASIC and attached endpoints.

Use Value: Meets PCIe Gen 4 common-clock jitter spec without external jitter cleaners; eliminates need for four discrete XOs and reduces layout complexity.

Use Scenario: Generating 156.25 MHz and 312.5 MHz clocks for 10GbE KR and 25GbE KR PHYs in telecom line cards.

IC Role / Device Role / Timing Role: Dual-frequency, dual-format clock source with independent LVDS and CML outputs driving backplane and chip-to-chip links.

Use Value: Single-device solution replaces two oscillators and one buffer; supports both IEEE 802.3bj and 802.3by timing requirements with shared reference stability.

Broadcast Video Frame Sync

FPGA-Based Video Processing

Use Scenario: Delivering genlock-capable 27 MHz, 74.25 MHz, and 148.5 MHz clocks to SDI transmitters, receivers, and frame synchronizers in broadcast infrastructure.

IC Role / Device Role / Timing Role: Multi-format clock synthesizer with sub-ns phase alignment across outputs for SMPTE ST 2081-10 compliance.

Use Value: Achieves <100 ps inter-output skew and programmable initial phase offset (±45 ns) - enables precise video pipeline synchronization without external delay lines.

Use Scenario: Supplying 50 MHz system clock, 200 MHz DDR3 interface clock, and 300 MHz video processing clock to Xilinx Zynq Ultrascale+ MPSoC.

IC Role / Device Role / Timing Role: Configurable clock hub with CMOS, LVDS, and SSTL outputs matched to FPGA I/O standards and voltage domains.

Use Value: Eliminates three discrete clock sources; supports simultaneous 1.8 V (FPGA core), 2.5 V (DDR3), and 3.3 V (legacy peripherals) supply rails via independent VDDO banks.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D05866-GM	Higher integration: 8 outputs, lower jitter (0.35 ps RMS), integrated LDOs, smaller 3.2 × 3.2 mm package	Targets higher-density systems requiring >4 clocks or tighter jitter budgets (e.g., 5G baseband, AI accelerators)	Select when needing ≥8 outputs, sub-0.4 ps jitter, or space-constrained designs; requires updated layout and ClockBuilder Pro v3.x
ICS853S01AG-01T	Fixed-frequency, non-programmable; 4 LVDS outputs; 1.2 ps RMS jitter; 3.3 V only; no spread spectrum or phase adjustment	Cost-sensitive, volume production where frequencies are static and jitter margin >0.7 ps is acceptable	Select for simple, low-cost replacement of fixed-frequency XO arrays where flexibility and advanced features are unnecessary

Compared with Si5332A-D05866-GM, SI5338N-B05866-GMR offers broader input reference support (crystal + 5–710 MHz) and simpler I²C register map, while ICS853S01AG-01T provides lower unit cost but lacks programmability, spread spectrum, and PCIe Gen 4 compliance - making SI5338N-B05866-GMR optimal for flexible, high-performance timing in evolving system architectures.

Availability

SI5338N-B05866-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, 10/25GbE PHY clocking, and broadcast video frame sync applications requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.

Supply support for SI5338N-B05866-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and mobile markets.

The SI5338N-B05866-GMR belongs to Skyworks' Si5338 family of programmable clock generators, designed specifically for high-speed serial interface timing in datacenter, telecom, and broadcast equipment where low jitter, multi-format flexibility, and PCIe compliance are critical.

FAQ

What is the maximum output frequency supported by the SI5338N-B05866-GMR?

The SI5338N-B05866-GMR supports differential output frequencies up to 710 MHz (LVPECL/LVDS/CML), 250 MHz (HCSL), and 350 MHz (SSTL/HSTL), with single-ended CMOS outputs up to 200 MHz. These limits are defined by the MultiSynth™ VCO range and output driver bandwidth - exceeding them degrades jitter and signal integrity. For frequencies above 350 MHz, only two unique outputs may operate simultaneously (Fvco/4 and Fvco/6 modes).

Does the SI5338N-B05866-GMR support PCIe Gen 4 Separate Reference No Spread (SRNS) mode?

Yes, the SI5338N-B05866-GMR is compliant with PCIe Gen 4 SRNS mode, achieving 0.11–0.32 ps RMS jitter under specified conditions (PLL BW 2–4 MHz, CDR = 10 MHz). This is validated using the Skyworks PCIe Clock Jitter Tool and meets PCI-SIG Base Specification 4.0 rev 0.5. Configuration requires setting appropriate loop bandwidth and disabling spread spectrum on the target output.

Can the SI5338N-B05866-GMR generate different output voltages on each channel?

Yes, the SI5338N-B05866-GMR provides independent output buffer supplies (VDDO0–VDDO3), each configurable from 1.4 V to 3.63 V. This enables simultaneous LVDS (2.5 V), HCSL (1.8 V), and CMOS (3.3 V) outputs - supporting heterogeneous interface standards without external level translators. Voltage selection is per-output bank, not per-pin.

How is the SI5338N-B05866-GMR programmed, and what software is required?

The SI5338N-B05866-GMR is programmed via its I²C/SMBus-compatible interface using Skyworks' ClockBuilder Pro software. This GUI-based tool generates custom configuration files (.cbs), validates timing constraints, and supports field reprogramming over I²C. Factory OTP programming is also available. No external microcontroller is needed for basic configuration - all registers are accessible through standard I²C writes.

What is the thermal performance of the SI5338N-B05866-GMR in continuous operation?

The SI5338N-B05866-GMR has a junction-to-ambient thermal resistance (θJA) of 37 °C/W under still-air conditions and junction-to-case (θJC) of 10 °C/W. At 45 mA core current and full 4-output load, junction temperature rise is ~1.7 °C above ambient - well within the –40 to +85 °C operating range. Recommended PCB land pattern includes thermal via array under the exposed pad for optimal heat dissipation.

SI5338N-B05866-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338N-B05866-GMR FAQ

1.How can I place an order for SI5338N-B05866-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338N-B05866-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338N-B05866-GMR reliable?

The price and inventory of SI5338N-B05866-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338N-B05866-GMR is usually 5 days.

3.What payment methods are accepted for SI5338N-B05866-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338N-B05866-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338N-B05866-GMR?

SI5338N-B05866-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338N-B05866-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338N-B05866-GMR?

For technical support, including SI5338N-B05866-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338N-B05866-GMR requirements.

6.How does Aetrix verify that SI5338N-B05866-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338N-B05866-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338N-B05866-GMR meets industry standards.

7.What is the process for return or replacement of SI5338N-B05866-GMR?

All SI5338N-B05866-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338N-B05866-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338N-B05866-GMR part is unused and in its original packaging.

Return procedure for SI5338N-B05866-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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