Skyworks Solutions Inc. SI5338N-B05879-GMR

Overview

SI5338N-B05879-GMR from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation across –40 to +85 °C. It replaces up to four crystal oscillators in FPGA clocking, PCIe interconnect, and broadcast video timing systems.

For engineers reviewing the SI5338N-B05879-GMR datasheet, SI5338N-B05879-GMR pinout, SI5338N-B05879-GMR application, or SI5338N-B05879-GMR equivalent, key selection criteria include its MultiSynth™-based any-frequency synthesis (0.16–710 MHz per output), independent output voltage support (1.5/1.8/2.5/3.3 V), spread-spectrum capability (0.5–5.0% down-spread), and 24-QFN package with I²C/SMBus programmability.

Technical Context

The SI5338N-B05879-GMR implements a two-stage PLL architecture: a high-stability reference stage followed by four independent MultiSynth™ fractional-N synthesis blocks, each driving a configurable output buffer. Its input flexibility supports crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), and differential (5–710 MHz) references.

Each output driver supports LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats with independent voltage rails (VDDO0–VDDO3), programmable phase offset (<20 ps step resolution), and glitchless frequency increment/decrement in 1 ppm steps. External feedback mode enables zero-delay operation, while loss-of-lock and loss-of-signal alarms provide system monitoring.

Key Specifications

Pinout & Package

SI5338N-B05879-GMR is housed in a 24-lead, 4 × 4 mm QFN package with exposed thermal pad. Pin 1 is top-left corner (IN1), pin 24 is bottom-right (GND). The package supports reflow soldering per JEDEC J-STD-020 (peak 260 °C).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Compared with Si5338A-B-GM and ICS853S01AGI-01LFT, SI5338N-B05879-GMR uniquely combines field-programmable MultiSynth™ synthesis, PCIe Gen 4 jitter compliance, and per-output voltage/format control - making it optimal for adaptive, multi-standard timing architectures requiring post-silicon configuration.

Availability

SI5338N-B05879-GMR is available at Aetrix Electronics and suitable for PCIe interconnect, FPGA clocking, and broadcast video timing applications requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for SI5338N-B05879-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5338 product line delivers programmable, low-jitter clock generation for high-speed digital systems - designed specifically to replace multiple fixed-frequency oscillators while meeting stringent PCIe, Ethernet, and telecom timing standards.

FAQ

What is the primary function of the SI5338N-B05879-GMR?

The SI5338N-B05879-GMR is an I²C-programmable quad clock generator that synthesizes four independent, low-jitter output clocks from a single reference input. Its core function is to replace up to four discrete oscillators in systems such as PCIe switches, FPGAs, and broadcast equipment - delivering 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 compliance, and flexible output formatting. SI5338N-B05879-GMR uses Skyworks' MultiSynth™ technology to achieve true zero-ppm frequency accuracy on all outputs.

Does the SI5338N-B05879-GMR support PCIe Gen 4 timing requirements?

Yes, the SI5338N-B05879-GMR meets PCIe Gen 4 Common Clock jitter specifications with 0.15–0.45 ps RMS jitter (10 kHz–50 MHz bandwidth) when configured per Skyworks' recommended settings, including PLL bandwidth of 2–4 MHz and CDR = 10 MHz. It is explicitly validated for PCIe Gen 4 in the official datasheet (Rev. 1.6, Table 12), and its jitter performance is verified using the Skyworks PCIe Clock Jitter Tool. SI5338N-B05879-GMR also satisfies Gen 3 SRNS requirements.

How many output formats does the SI5338N-B05879-GMR support, and can they be mixed?

The SI5338N-B05879-GMR supports six output signal formats: LVPECL, LVDS, HCSL, CMOS, SSTL, and HSTL - and all four outputs can be independently configured with different formats and supply voltages (VDDO0–VDDO3 = 1.4–3.63 V). This enables mixed-signal interfacing, such as driving an LVDS SerDes, an HCSL memory controller, a CMOS microcontroller, and an SSTL FPGA I/O bank simultaneously. SI5338N-B05879-GMR's per-output configurability eliminates level-shifter components in complex timing trees.

What reference inputs are compatible with the SI5338N-B05879-GMR?

The SI5338N-B05879-GMR accepts four types of reference inputs: (1) 8–30 MHz fundamental-mode crystals connected to IN1/IN2, (2) 5–200 MHz CMOS clocks on IN3/IN4, (3) 5–350 MHz SSTL/HSTL signals, and (4) 5–710 MHz differential inputs on IN1/IN2 or IN5/IN6. All inputs support loss-of-signal detection with 2.6–5 µs response time. SI5338N-B05879-GMR's flexible input architecture allows seamless integration with existing clock sources across telecom, computing, and video platforms.

Is the SI5338N-B05879-GMR pin-compatible with other Si5338 variants?

Yes, all Si5338 variants - including SI5338N-B05879-GMR - share identical 24-QFN pinouts and footprint, as confirmed in the Skyworks datasheet Section 8 ("Device Pinout by Part Number"). Pin assignments for IN1, CLK0A/B through CLK3A/B, VDDOx, SCL/SDA, and INTR are fixed across the family. However, factory-programmed variants (e.g., Si5338A-B-GM) may differ in OTP content and default configuration; SI5338N-B05879-GMR retains full I²C programmability and user-defined NVM settings.