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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338N-B05936-GMR

Name: SI5338N-B05936-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338N-B05936-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338N-B05936-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338N-B05936-GMR.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5338N-B05936-GMR from Skyworks Solutions is a quad-output, I²C-programmable clock generator implementing MultiSynth™ frequency synthesis with 0 ppm precision per output. It delivers four independent differential or single-ended clocks (LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL) across 0.16–710 MHz, supports PCIe Gen 1–4 common clock and SRNS compliance, and operates from 1.8/2.5/3.3 V core supply in a 4 × 4 mm 24-QFN package for FPGA, processor, and Ethernet switch timing.

For engineers reviewing the SI5338N-B05936-GMR datasheet, SI5338N-B05936-GMR pinout, SI5338N-B05936-GMR application, or SI5338N-B05936-GMR equivalent, key selection considerations include its 0.7 ps RMS typical phase jitter, independent per-output voltage (1.5–3.3 V), programmable phase/frequency step resolution (<20 ps / 1 ppm), spread-spectrum capability (0.5–5.0% at 33–63 kHz), and support for external crystal (8–30 MHz) or wide-band differential inputs (5–710 MHz).

Technical Context

The SI5338N-B05936-GMR integrates a dual-stage PLL architecture: a high-stability reference stage (with crystal or external input) feeding a fractional-N VCO, followed by four independent MultiSynth™ synthesis blocks-each with configurable R/M/N dividers and output format selection. This enables true any-frequency generation without integer constraints on individual outputs.

Each of the four output drivers supports independent configuration of signal format (LVPECL, LVDS, HCSL, CMOS, SSTL, HSTL), output supply voltage (1.5/1.8/2.5/3.3 V), phase offset (±45 ns in <20 ps steps), and spread-spectrum modulation (5–350 MHz, 0.5–5.0%, 33–63 kHz). Loss-of-lock and loss-of-signal alarms are implemented via dedicated INTR pin.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 3/4 SRNS and GbE jitter requirements
Output Frequency Range	0.16–710 MHz per channel; supports up to two >350 MHz outputs simultaneously (Fvco/4 & Fvco/6)
Input Reference Support	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz)
Output Format Flexibility	Four differential (LVPECL/LVDS/HCSL/CML) or eight single-ended (CMOS/SSTL/HSTL) outputs, or mixed
Supply Voltage Range	Core: 1.8/2.5/3.3 V ±10%; Output buffers: 1.4–3.63 V independently configurable per driver
Temperature Range	–40 °C to +85 °C; qualified for industrial embedded and telecom line card operation
Power Consumption	45 mA typical core current at 100 MHz on all outputs and 25 MHz refclk

Pinout & Package

SI5338N-B05936-GMR is housed in a 4 × 4 mm, 24-lead QFN package with exposed thermal pad. Pin assignments follow Skyworks' standard Si5338 layout: dual differential inputs (IN1/IN2, IN5/IN6), two single-ended inputs (IN3, IN4), four differential output pairs (CLK0A/B through CLK3A/B), four independent VDDOx supplies, I²C interface (SCL/SDA), interrupt (INTR), and power/ground rails.

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2	Differential input pair #1	Accepts 5–710 MHz AC-coupled differential clock; internal 100 Ω termination enabled
IN3, IN4	Single-ended input pins	Support CMOS/SSTL/HSTL inputs (5–350 MHz); VIH/VIL referenced to VDD
CLK0A, CLK0B	Differential output pair #0	Configurable format (LVPECL/LVDS/HCSL/CML); driven by MultiSynth₀; VDDO0 supply
CLK1A, CLK1B	Differential output pair #1	Independent synthesis path (MultiSynth₁); supports same formats and voltage as CLK0
CLK2A, CLK2B	Differential output pair #2	MultiSynth₂-driven; full format and voltage configurability; no shared resources with other outputs
CLK3A, CLK3B	Differential output pair #3	MultiSynth₃-driven; supports independent phase/frequency adjustment and SSC
SCL, SDA	I²C serial interface	SMBus-compatible; supports standard/fast-mode (100/400 kHz); used for register programming and status readback
INTR	Interrupt output	Open-drain active-low signal indicating loss-of-lock or loss-of-signal events
VDDO0–VDDO3	Output buffer supplies	Independent 1.4–3.63 V supplies per output bank; enable mixed-voltage system interfacing
VDD	Core supply	1.8/2.5/3.3 V ±10%; powers PLL, synthesizers, and control logic
GND, RSVD_GND	Ground connections	Multiple ground pins including reserved ground for noise isolation; requires solid thermal pad connection

Key Features

Feature	Design Value
MultiSynth™ Any-Frequency Synthesis	Four independent synthesis engines enabling zero-ppm accuracy on each output without shared dividers or frequency constraints
PCIe Gen 1–4 Compliance	Meets Common Clock and Gen 3 SRNS jitter specs (0.11–0.45 ps RMS); validated with Intel Clock Jitter Tool
Per-Output Voltage & Format Control	Each output bank (VDDO0–VDDO3) independently set to 1.5/1.8/2.5/3.3 V and assigned LVPECL, LVDS, HCSL, CMOS, SSTL, or HSTL
Programmable Phase/Frequency Adjustment	Glitchless real-time tuning in <20 ps phase steps and 1 ppm frequency increments via pin or I²C control
Spread-Spectrum Clocking (SSC)	Configurable on any output: 5–350 MHz range, 0.5–5.0% spread, 33–63 kHz modulation rate for EMI reduction
External Feedback Mode	Enables zero-delay buffer operation by routing CLKOUT back to feedback input, bypassing PLL for minimal propagation delay (2.5–4 ns)

Applications

Ethernet Switch Timing	PCIe Gen 4 Server Interconnect
Use Scenario: High-density 10/25/100 GbE switch fabric requiring low-jitter, multi-frequency clocking for SerDes lanes, MAC, and CPU interfaces. IC Role / Device Role / Timing Role: Quad clock generator providing independent 156.25 MHz (XAUI), 312.5 MHz (CAUI), 100 MHz (CPU), and 25 MHz (management) clocks with <0.7 ps RMS jitter. Use Value: Eliminates four discrete oscillators; enables per-lane jitter optimization and dynamic frequency scaling during link training.	Use Scenario: Dual-CPU server motherboard with PCIe Gen 4 x16 slots, NVMe storage, and PLX switches demanding strict common-clock jitter compliance. IC Role / Device Role / Timing Role: Generates 100 MHz common reference for all PCIe endpoints plus 100 MHz SRNS clock, both meeting PCIe Gen 4 0.45 ps RMS requirement. Use Value: Single-device solution replaces multiple oscillators and jitter cleaners; supports simultaneous Gen 4 and legacy Gen 1–3 links.
Broadcast Video Synchronization	FPGA-Based Test Equipment
Use Scenario: SMPTE ST 2082/2110 IP video router requiring precise 27 MHz, 74.25 MHz, and 148.5 MHz pixel clocks with sub-ns skew across 32+ outputs. IC Role / Device Role / Timing Role: Configured in buffered mode with external 27 MHz crystal; generates three synchronized frequencies using integer-related MultiSynth ratios. Use Value: Achieves <100 ps output-to-output skew and <0.7 ps RMS jitter-critical for lip-sync and frame-accurate switching.	Use Scenario: High-speed digital pattern generator using Xilinx Kintex Ultrascale+ FPGA needing four precisely phased clocks (125 MHz, 250 MHz, 500 MHz, 1 GHz) for parallel test vectors. IC Role / Device Role / Timing Role: Provides four independent, phase-aligned clocks with programmable offsets (±45 ns in <20 ps steps) and identical jitter performance. Use Value: Enables deterministic timing margin testing across voltage/temperature corners without external delay lines or multiple ICs.

Ethernet Switch Timing

PCIe Gen 4 Server Interconnect

Use Scenario: High-density 10/25/100 GbE switch fabric requiring low-jitter, multi-frequency clocking for SerDes lanes, MAC, and CPU interfaces.

IC Role / Device Role / Timing Role: Quad clock generator providing independent 156.25 MHz (XAUI), 312.5 MHz (CAUI), 100 MHz (CPU), and 25 MHz (management) clocks with <0.7 ps RMS jitter.

Use Value: Eliminates four discrete oscillators; enables per-lane jitter optimization and dynamic frequency scaling during link training.

Use Scenario: Dual-CPU server motherboard with PCIe Gen 4 x16 slots, NVMe storage, and PLX switches demanding strict common-clock jitter compliance.

IC Role / Device Role / Timing Role: Generates 100 MHz common reference for all PCIe endpoints plus 100 MHz SRNS clock, both meeting PCIe Gen 4 0.45 ps RMS requirement.

Use Value: Single-device solution replaces multiple oscillators and jitter cleaners; supports simultaneous Gen 4 and legacy Gen 1–3 links.

Broadcast Video Synchronization

FPGA-Based Test Equipment

Use Scenario: SMPTE ST 2082/2110 IP video router requiring precise 27 MHz, 74.25 MHz, and 148.5 MHz pixel clocks with sub-ns skew across 32+ outputs.

IC Role / Device Role / Timing Role: Configured in buffered mode with external 27 MHz crystal; generates three synchronized frequencies using integer-related MultiSynth ratios.

Use Value: Achieves <100 ps output-to-output skew and <0.7 ps RMS jitter-critical for lip-sync and frame-accurate switching.

Use Scenario: High-speed digital pattern generator using Xilinx Kintex Ultrascale+ FPGA needing four precisely phased clocks (125 MHz, 250 MHz, 500 MHz, 1 GHz) for parallel test vectors.

IC Role / Device Role / Timing Role: Provides four independent, phase-aligned clocks with programmable offsets (±45 ns in <20 ps steps) and identical jitter performance.

Use Value: Enables deterministic timing margin testing across voltage/temperature corners without external delay lines or multiple ICs.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D05936-GM	Higher integration: 8 outputs, integrated LDOs, lower jitter (0.35 ps RMS), supports JESD204B deterministic latency	Targets JESD204B-compliant data converters and 5G radio units where deterministic latency and ultra-low jitter are mandatory	Choose when >4 outputs, sub-0.4 ps jitter, or JESD204B sync is required; higher cost and larger 5×5 mm package
ICS8430I-01T	Fixed-function quad LVDS generator; no I²C programming; 0.9 ps RMS jitter; 0.1–700 MHz range; 3.3 V only	Used in cost-sensitive, high-volume applications like consumer NAS where frequency flexibility is not needed	Choose for fixed-frequency, low-cost deployments where reprogramming and multi-voltage support are unnecessary

Compared with Si5332A-D05936-GM, SI5338N-B05936-GMR offers broader input flexibility (crystal + wide-band differential/SE inputs) and lower BOM cost, while ICS8430I-01T provides simpler qualification but lacks programmability and voltage scalability-making SI5338N-B05936-GMR optimal for mid-complexity industrial and telecom designs requiring field-upgradable timing.

Availability

SI5338N-B05936-GMR is available at Aetrix Electronics and suitable for Ethernet switch/router, PCIe Gen 1–4 interconnect, and broadcast video timing applications requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for SI5338N-B05936-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and mobile markets.

The Si5338 product line was designed for high-performance, software-configurable clock generation in space-constrained systems-enabling consolidation of multiple oscillators into a single, field-programmable device for FPGA, processor, and high-speed serial interface timing.

FAQ

What is the default factory configuration of the SI5338N-B05936-GMR?

The SI5338N-B05936-GMR ships pre-programmed with a default configuration: 100 MHz LVDS outputs on all four channels, driven from an internal 25 MHz crystal oscillator, with VDDO supplies set to 2.5 V and I²C address 0x70. This allows immediate evaluation without programming; full customization requires ClockBuilder Pro software and I²C access.

Does the SI5338N-B05936-GMR support PCIe Gen 4 Separate Reference No Spread (SRNS) mode?

Yes, the SI5338N-B05936-GMR supports PCIe Gen 4 SRNS mode with 0.11–0.32 ps RMS jitter (typical), verified per PCI-SIG Base Specification 4.0 rev. 0.5. It achieves this using a 2–5 MHz PLL bandwidth and 10 MHz CDR reference; configuration requires setting specific MultiSynth divider values and disabling spread spectrum on the SRNS output.

Can the SI5338N-B05936-GMR generate four different frequencies simultaneously above 350 MHz?

No-the SI5338N-B05936-GMR can output only two unique frequencies above 350 MHz simultaneously (Fvco/4 and Fvco/6), as constrained by its VCO architecture. All four outputs may operate above 350 MHz only if two share Fvco/4 and two share Fvco/6; independent >350 MHz frequencies require external fanout buffers or alternate timing ICs.

How is spread-spectrum clocking (SSC) configured on the SI5338N-B05936-GMR?

SSC is configured per output via ClockBuilder Pro or direct I²C register writes to the SSC control registers (0x142–0x145). Parameters include center-spread (0.5–5.0%), modulation rate (33–63 kHz), and direction (down-spread default). The SI5338N-B05936-GMR applies SSC only to the selected MultiSynth output stage, preserving base jitter performance on non-SSC outputs.

What is the minimum input frequency supported in PLL bypass (clock buffer) mode for the SI5338N-B05936-GMR?

In PLL bypass mode, the SI5338N-B05936-GMR supports input frequencies down to 1 MHz on single-ended inputs (IN3/IN4) and 5 MHz on differential inputs (IN1/IN2, IN5/IN6). However, loss-of-signal detection is disabled below 5 MHz, and additive phase jitter increases slightly-0.165 ps RMS typical at 622.08 MHz drops to ~0.25 ps RMS at 10 MHz.

SI5338N-B05936-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338N-B05936-GMR FAQ

1.How can I place an order for SI5338N-B05936-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338N-B05936-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338N-B05936-GMR reliable?

The price and inventory of SI5338N-B05936-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338N-B05936-GMR is usually 5 days.

3.What payment methods are accepted for SI5338N-B05936-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338N-B05936-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338N-B05936-GMR?

SI5338N-B05936-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338N-B05936-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338N-B05936-GMR?

For technical support, including SI5338N-B05936-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338N-B05936-GMR requirements.

6.How does Aetrix verify that SI5338N-B05936-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338N-B05936-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338N-B05936-GMR meets industry standards.

7.What is the process for return or replacement of SI5338N-B05936-GMR?

All SI5338N-B05936-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338N-B05936-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338N-B05936-GMR part is unused and in its original packaging.

Return procedure for SI5338N-B05936-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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