Skyworks Solutions Inc. SI5338N-B06022-GMR
- Part No.:
- SI5338N-B06022-GMR
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Application Specific Clock/Timing
- Package:
- 24-VFQFN Exposed Pad
- Datasheet:
-
SI5338N-B06022-GMR.pdf
- Description:
- I2C CONTROL, 4-OUTPUT, ANY FREQU
- Quantity:
- Payment:

- Shipping:

Inventory:3,791
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SI5338N-B06022-GMR from Skyworks Solutions is a quad-output, I²C-programmable clock generator with MultiSynth™ frequency synthesis. It delivers four independent, any-frequency outputs (0.16–710 MHz), supports LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats, achieves 0.7 ps RMS phase jitter, and operates from 1.8/2.5/3.3 V core supply in PCIe Gen 4–compliant timing systems.
For engineers reviewing the SI5338N-B06022-GMR datasheet, SI5338N-B06022-GMR pinout, SI5338N-B06022-GMR application, or SI5338N-B06022-GMR equivalent, this device enables precise multi-clock domain synchronization in high-speed serial interfaces, FPGA/processor clocking, and broadcast video timing where zero-ppm accuracy and sub-picosecond jitter are critical.
Technical Context
The SI5338N-B06022-GMR integrates a dual-stage PLL architecture: a reference-stage PLL locks to one of six input sources (crystal, CMOS, SSTL, or differential), followed by four independent MultiSynth™ fractional-N synthesizers per output. Each synthesizer supports integer/fractional mode operation with programmable R, M, N, P dividers and real-time frequency/phase adjustment via I²C or dedicated pins.
It features loss-of-signal and loss-of-lock detection, independent output voltage control (1.5/1.8/2.5/3.3 V), spread-spectrum modulation (0.5–5.0% at 33–63 kHz), and external feedback for zero-delay mode. The device operates across –40 to +85 °C and meets PCIe Gen 1–4 Common Clock and Gen 3 SRNS jitter requirements.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output count | Four independent differential or single-ended clock outputs (CLK0A/B through CLK3A/B) |
| Frequency range | 0.16–710 MHz per output; supports up to two >350 MHz frequencies simultaneously (Fvco/4 and Fvco/6) |
| Phase jitter (RMS) | 0.7 ps typical (12 kHz–20 MHz); compliant with PCIe Gen 4 common clock and OC-12 specs |
| Input flexibility | Supports 8–30 MHz crystal, 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL, or 5–710 MHz differential reference |
| Supply voltage | Core: 1.8/2.5/3.3 V ±10%; output buffers: independently configurable 1.4–3.63 V per driver |
| Package | 24-pin QFN, 4 × 4 mm, 0.5 mm pitch, exposed thermal pad |
| Operating temperature | –40 °C to +85 °C ambient; junction-to-ambient thermal resistance θJA = 37 °C/W |
Pinout & Package
SI5338N-B06022-GMR uses a 24-pin QFN package (4 × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin assignments are fixed per Skyworks Si5338 family specification.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN1, IN2 | Differential input pair 1 | Accepts 5–710 MHz AC-coupled differential clock; requires external 100 Ω termination |
| IN3, IN4 | Single-ended input pair | Accepts 5–200 MHz CMOS-level clock; VIH ≥ 0.7×VDD, VIL ≤ 0.3×VDD |
| IN5, IN6 | Differential input pair 2 | Second 5–710 MHz differential input path; identical electrical specs to IN1/IN2 |
| CLK0A, CLK0B | Differential output 0 | LVPECL/LVDS/HCSL/CML-compatible; independently configurable format and voltage |
| CLK1A, CLK1B | Differential output 1 | Same configurability as CLK0; supports independent frequency, phase, and SSC settings |
| CLK2A, CLK2B | Differential output 2 | Programmable output with full MultiSynth™ synthesis and phase increment/decrement |
| CLK3A, CLK3B | Differential output 3 | Fourth independent output; supports <20 ps phase step resolution and 1 ppm frequency steps |
| VDDO0–VDDO3 | Output buffer supplies | Four independent 1.4–3.63 V supplies - one per output pair - enabling mixed-voltage clock domains |
| VDD | Core supply | Single 1.8/2.5/3.3 V supply powering PLL, logic, and memory; PSRR optimized |
| SCL, SDA | I²C interface | SMBus-compatible 100/400 kHz interface for configuration and status readback |
| INTR | Interrupt output | Open-drain alarm signal indicating loss-of-lock or loss-of-signal events |
Key Features
| Feature | Design Value |
|---|---|
| MultiSynth™ synthesis | Four independent fractional-N synthesizers enable true zero-ppm frequency accuracy on all outputs |
| Glitchless frequency tuning | Independent PINC/FINC pins allow real-time 1 ppm frequency increments/decrements without output interruption |
| Sub-20 ps phase control | Programmable initial phase offset (±45 ns) and <20 ps phase step resolution per output |
| PCIe Gen 4 compliance | 0.15–0.45 ps RMS jitter in PCIe Gen 4 common clock mode; validated per PCI-SIG Base Spec 4.0 rev 0.5 |
| Flexible spread spectrum | Configurable SSC on any output: 0.5–5.0% spread, 33–63 kHz modulation rate, down-spread default |
Applications
| Ethernet Switch/Routing | PCIe Gen 1–4 Timing |
|---|---|
Use Scenario: 10 GbE line cards requiring synchronous multi-port clocking with deterministic skew control. IC Role / Device Role / Timing Role: Quad clock generator providing independent 156.25 MHz, 312.5 MHz, and 625 MHz clocks to PHYs, MACs, and switch fabric. Use Value: Eliminates four discrete oscillators; maintains <100 ps output-to-output skew and 0.7 ps RMS jitter for IEEE 802.3bj compliance. |
Use Scenario: Server motherboard with CPU, GPU, and NVMe SSD sharing PCIe Gen 4 root complex timing. IC Role / Device Role / Timing Role: Common clock source delivering 100 MHz differential HCSL to all PCIe slots and controllers. Use Value: Meets PCIe Gen 4 common clock TJ <33.6 ps pk-pk and RMS jitter <0.45 ps; supports SRNS mode for Gen 3 endpoints. |
| Broadcast Video/Audio Timing | FPGA & Processor Clocking |
Use Scenario: SMPTE ST 2082-1 12G-SDI transport equipment needing genlock-capable reference distribution. IC Role / Device Role / Timing Role: Synthesizes 74.25 MHz, 148.5 MHz, and 297 MHz video clocks from a 27 MHz master reference. Use Value: Achieves <0.7 ps RMS jitter and programmable phase alignment across outputs for frame-accurate genlock. |
Use Scenario: High-end industrial FPGA-based data acquisition system with ADC sampling, DDR4 memory, and PCIe host interface. IC Role / Device Role / Timing Role: Generates 500 MHz ADC sampling clock, 1200 MHz DDR4 clock, and 100 MHz PCIe reference from single crystal. Use Value: Replaces three separate clock ICs; enables independent voltage scaling (1.8 V for DDR4, 3.3 V for PCIe) and dynamic frequency scaling. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad-output clock generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5338A-B06022-GM | Same pinout and register map; factory-programmed OTP instead of blank NVM; no field reprogramming capability | Fixed configuration only; suitable for high-volume production where clock tree is finalized pre-deployment | Select when firmware-controlled runtime reconfiguration is unnecessary and cost sensitivity favors OTP over flash-based NVM |
| LMK04832RHAT | Two PLLs with JESD204B support; higher power (120 mA typical); larger 48-QFN package; no integrated crystal oscillator circuitry | Targeted at RF/data converter timing; includes JESD204B SYSREF and deterministic latency features not present in Si5338 | Select when JESD204B subclass 1 timing, ultra-low deterministic latency, or dual-loop clean-up is required over flexible any-frequency synthesis |
Compared with SI5338N-B06022-GMR, the Si5338A-B06022-GM offers identical performance in a factory-configured form, while the LMK04832RHAT adds JESD204B-specific features at the cost of higher power, larger footprint, and reduced input flexibility - making SI5338N-B06022-GMR optimal for general-purpose multi-frequency clock generation with field programmability.
Availability
SI5338N-B06022-GMR is available at Aetrix Electronics and suitable for Ethernet switching, PCIe Gen 4 infrastructure, and broadcast video timing requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.
Supply support for SI5338N-B06022-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.
The Si5338 product line delivers programmable, low-jitter clock generation for high-speed serial interfaces, FPGA/ASIC clock trees, and multi-protocol timing systems where flexibility, precision, and space efficiency are essential.
FAQ
What is the primary function of the SI5338N-B06022-GMR?
The SI5338N-B06022-GMR is an I²C-programmable quad clock generator using Skyworks' MultiSynth™ technology to synthesize four independent, any-frequency output clocks (0.16–710 MHz) with 0.7 ps RMS phase jitter. It replaces multiple discrete oscillators in systems requiring precise, configurable timing - such as PCIe Gen 4, 10 GbE, and broadcast video equipment - and is delivered in a 4 × 4 mm 24-QFN package.
Does the SI5338N-B06022-GMR support PCIe Gen 4 timing requirements?
Yes, the SI5338N-B06022-GMR meets PCIe Gen 4 common clock specifications with 0.15–0.45 ps RMS jitter (10 kHz–50 MHz) and total jitter <33.6 ps pk-pk. It is validated per PCI-SIG Base Specification 4.0 rev 0.5 and supports both common clock and Gen 3 SRNS modes. Skyworks provides the PCIe Clock Jitter Tool for in-system validation of SI5338N-B06022-GMR performance.
Can the SI5338N-B06022-GMR generate different output voltages simultaneously?
Yes, the SI5338N-B06022-GMR supports independent output buffer supply voltages (VDDO0–VDDO3) ranging from 1.4 V to 3.63 V. This allows simultaneous generation of LVDS (2.5 V), HCSL (1.8 V), and CMOS (3.3 V) outputs from a single device - enabling mixed-voltage clock domains without level-shifting components in FPGA, processor, and memory subsystems.
How is the SI5338N-B06022-GMR configured and programmed?
The SI5338N-B06022-GMR is configured via its I²C/SMBus-compatible interface (SCL/SDA pins) using Skyworks' ClockBuilder Pro software. This GUI tool generates custom configuration files, validates timing constraints, and writes settings directly to the device's on-chip NVM. Factory programming and field updates are both supported, and pin-controlled frequency/phase adjustments (PINC/FDEC) are available for real-time tuning without I²C traffic.
What input reference sources does the SI5338N-B06022-GMR accept?
The SI5338N-B06022-GMR accepts six input reference types: 8–30 MHz crystal (on-chip load capacitance), 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL, and 5–710 MHz differential (IN1/IN2 or IN5/IN6). All inputs support loss-of-signal detection, and the device can operate in PLL mode or bypass mode (buffer-only) with propagation delay <4 ns. No external PLL components are required.
SI5338N-B06022-GMR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- MultiSynth™
- Package/Case:
- 24-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- PLL:
- -
- Main Purpose:
- -
- Input:
- -
- Output:
- -
- Number of Circuits:
- -
- Ratio - Input:Output:
- -
- Differential - Input:Output:
- -
- Frequency - Max:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 24-QFN (4x4)
SI5338N-B06022-GMR FAQ
1.How can I place an order for SI5338N-B06022-GMR through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5338N-B06022-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5338N-B06022-GMR reliable?
The price and inventory of SI5338N-B06022-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338N-B06022-GMR is usually 5 days.
3.What payment methods are accepted for SI5338N-B06022-GMR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338N-B06022-GMR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5338N-B06022-GMR?
SI5338N-B06022-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5338N-B06022-GMR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5338N-B06022-GMR?
For technical support, including SI5338N-B06022-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338N-B06022-GMR requirements.
6.How does Aetrix verify that SI5338N-B06022-GMR is sourced from the original manufacturer or authorized distributors?
All SI5338N-B06022-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338N-B06022-GMR meets industry standards.
7.What is the process for return or replacement of SI5338N-B06022-GMR?
All SI5338N-B06022-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338N-B06022-GMR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5338N-B06022-GMR part is unused and in its original packaging.
Return procedure for SI5338N-B06022-GMR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SI5338N-B06022-GMR Tags

-
LMK00334RTVRQ1
Texas Instruments
.jpg)
-
DSC557-0344FI0T
Microchip Technology

-
9FGV0241AKILFT
Renesas

-
9DBL0452CKILFT
Renesas
.jpg)
-
DSC557-0344FL1T
Microchip Technology
-
RC19008AGND#KB0
Renesas
-
RC19008AGND#BB0
Renesas

-
9DB403DGILFT
Renesas

-
9DB233AGILFT
Renesas

-
9DB803DGILFT
Renesas

-
9FGL0851DKILFT
Renesas
-
AB-557-03-HCHC-F-L-C-T
Abracon LLC
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

