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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338N-B06121-GMR

Name: SI5338N-B06121-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338N-B06121-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338N-B06121-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338N-B06121-GMR.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5338N-B06121-GMR from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation from 1.8/2.5/3.3 V core supply in a 4 × 4 mm 24-QFN package. It replaces up to four crystal oscillators in high-speed serial interface timing applications.

For engineers reviewing the SI5338N-B06121-GMR datasheet, SI5338N-B06121-GMR pinout, SI5338N-B06121-GMR application, or SI5338N-B06121-GMR equivalent, key selection considerations include its MultiSynth™-based any-frequency synthesis (0.16–710 MHz per output), independent output voltage per driver (1.5/1.8/2.5/3.3 V), spread-spectrum capability (0.5–5.0% down-spread), and I²C/SMBus programmability with ClockBuilder Pro support.

Technical Context

The SI5338N-B06121-GMR implements a two-stage synthesis architecture: a PLL-based Stage 1 (with 1.6 MHz loop bandwidth) locks to one of six input references (crystal, CMOS, SSTL/HSTL, or differential), followed by four independent MultiSynth™ fractional-N dividers in Stage 2. Each output driver supports LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats with programmable slew rate and termination.

It features loss-of-lock and loss-of-signal alarms, independent phase adjustment (<20 ps steps), frequency increment/decrement (1 ppm steps), and external feedback mode for zero-delay operation. The device integrates OTP NVM for factory or field programming and supports glitchless frequency transitions via pin control or I²C.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps - meets PCIe Gen 3 SRNS and GbE jitter requirements at 125 MHz output
Output Frequency Range	0.16–710 MHz - supports PCIe 100 MHz HCSL, 156.25 MHz Ethernet, 125 MHz USB 3.0, and 333 MHz DDR4 clocks
Input Reference Support	8–30 MHz crystal, 5–710 MHz differential, 5–350 MHz SSTL/HSTL - enables flexible system clock tree design
Supply Voltages	VDD = 1.8/2.5/3.3 V ±10%; VDDOx = 1.4–3.63 V - allows mixed-voltage board-level integration
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch - compatible with standard reflow profiles and high-density PCB layouts
Operating Temperature	–40 °C to +85 °C - qualified for industrial and telecom line card environments
Core Supply Current	45 mA typ at 100 MHz on all outputs - enables low-power timing in power-constrained systems

Pinout & Package

SI5338N-B06121-GMR uses a 24-lead QFN package (4 mm × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin 1 is top-left corner (IN1), and pin numbering proceeds counterclockwise. The package supports standard JEDEC reflow and provides low-inductance ground paths via multiple GND pins (pins 19, 20, 23, 24) and dedicated VDD/VDDO supplies.

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2, IN5, IN6	Differential input pairs	Accept 5–710 MHz AC-coupled differential clocks; require external 100 Ω termination
IN3, IN4	Single-ended inputs	Support 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL with internal biasing
CLK0A/CLK0B – CLK3A/CLK3B	Differential output pairs	Four independent outputs; each configurable as LVPECL/LVDS/HCSL/CML with selectable VDDO
VDDO0–VDDO3	Output buffer supplies	Independent 1.5/1.8/2.5/3.3 V rails per output bank - enable mixed-signal level translation
SCL, SDA	I²C interface	Standard SMBus-compatible 100 kHz / 400 kHz bus; supports ClockBuilder Pro configuration
INTR	Interrupt output	Open-drain status signal indicating loss-of-lock or loss-of-signal events

Key Features

Feature	Design Value
Any-frequency synthesis	Four independent outputs each programmable from 0.16–710 MHz with true zero-ppm accuracy using MultiSynth™
PCIe Gen 1–4 compliance	Meets Common Clock (Gen 1/2/3/4) and Gen 3 SRNS jitter specs (0.11–0.45 ps RMS) without external filtering
Independent output voltage per driver	VDDOx set individually to 1.5/1.8/2.5/3.3 V - eliminates level-shifter ICs in multi-rail FPGA/ASIC designs
Glitchless frequency tuning	Pin-controlled 1 ppm step increments/decrements with <667 ns update time - enables real-time SERDES margin testing
Programmable spread spectrum	Configurable down-spread (0.5–5.0%) and modulation rate (33–63 kHz) on any output - reduces EMI in dense PCB layouts
Zero-delay mode	External feedback path enables synchronous clock distribution with sub-100 ps skew across outputs

Applications

PCIe Gen 3/4 Switch Timing	Ethernet Switch/Routing
Use Scenario: Providing synchronized 100 MHz HCSL reference clocks to multiple PCIe Gen 3/4 switch ICs in a 1U server backplane. IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent, low-jitter PCIe-compliant clocks with matched phase alignment. Use Value: Eliminates four discrete oscillators while meeting PCIe Gen 3 SRNS jitter spec (≤0.32 ps RMS) and enabling per-port spread-spectrum control.	Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10/25 GbE PHYs and MACs in a modular L2/L3 switch ASIC. IC Role / Device Role / Timing Role: Programmable frequency translator converting a common 25 MHz crystal into multiple Ethernet line-rate clocks. Use Value: Supports IEEE 802.3bj/802.3by jitter requirements with 0.7 ps RMS phase jitter and independent output format selection (LVDS/HCSL).
FPGA/ASIC Processor Clocking	Broadcast Video Timing
Use Scenario: Supplying core, I/O, and transceiver clocks to Xilinx Versal or Intel Agilex FPGAs in high-performance compute acceleration cards. IC Role / Device Role / Timing Role: Configurable quad clock source with independent voltage rails (1.8 V, 2.5 V, 3.3 V) and phase-adjustable outputs. Use Value: Enables precise setup/hold timing closure across heterogeneous FPGA domains using <20 ps phase step resolution and sub-100 ps inter-output skew.	Use Scenario: Delivering SMPTE ST 2082 (12G-SDI) 74.25 MHz, ST 2081 (6G-SDI) 148.5 MHz, and ST 292 (HD-SDI) 27 MHz clocks to video processing SoCs. IC Role / Device Role / Timing Role: Low-jitter any-frequency generator supporting broadcast-grade jitter masks (≤0.3 ps RMS over 12 kHz–20 MHz). Use Value: Meets SMPTE RP184 jitter compliance with 0.7 ps RMS typical phase noise and deterministic jitter <10 ps pk-pk in integer synthesis mode.

PCIe Gen 3/4 Switch Timing

Ethernet Switch/Routing

Use Scenario: Providing synchronized 100 MHz HCSL reference clocks to multiple PCIe Gen 3/4 switch ICs in a 1U server backplane.

IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent, low-jitter PCIe-compliant clocks with matched phase alignment.

Use Value: Eliminates four discrete oscillators while meeting PCIe Gen 3 SRNS jitter spec (≤0.32 ps RMS) and enabling per-port spread-spectrum control.

Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10/25 GbE PHYs and MACs in a modular L2/L3 switch ASIC.

IC Role / Device Role / Timing Role: Programmable frequency translator converting a common 25 MHz crystal into multiple Ethernet line-rate clocks.

Use Value: Supports IEEE 802.3bj/802.3by jitter requirements with 0.7 ps RMS phase jitter and independent output format selection (LVDS/HCSL).

FPGA/ASIC Processor Clocking

Broadcast Video Timing

Use Scenario: Supplying core, I/O, and transceiver clocks to Xilinx Versal or Intel Agilex FPGAs in high-performance compute acceleration cards.

IC Role / Device Role / Timing Role: Configurable quad clock source with independent voltage rails (1.8 V, 2.5 V, 3.3 V) and phase-adjustable outputs.

Use Value: Enables precise setup/hold timing closure across heterogeneous FPGA domains using <20 ps phase step resolution and sub-100 ps inter-output skew.

Use Scenario: Delivering SMPTE ST 2082 (12G-SDI) 74.25 MHz, ST 2081 (6G-SDI) 148.5 MHz, and ST 292 (HD-SDI) 27 MHz clocks to video processing SoCs.

IC Role / Device Role / Timing Role: Low-jitter any-frequency generator supporting broadcast-grade jitter masks (≤0.3 ps RMS over 12 kHz–20 MHz).

Use Value: Meets SMPTE RP184 jitter compliance with 0.7 ps RMS typical phase noise and deterministic jitter <10 ps pk-pk in integer synthesis mode.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D06121-GM	Higher integration: integrated crystal, lower jitter (0.35 ps RMS), 10-output capability, but larger 5 × 5 mm 32-QFN package	Preferred for space-constrained designs requiring ultra-low jitter and no external crystal	Select when absolute jitter performance and crystal integration outweigh cost and footprint constraints
ICS853S01AGI-01LFT	Fixed-frequency, non-programmable quad LVDS clock buffer; no MultiSynth™ synthesis; 1.2 ps RMS jitter; 3.3 V only	Limited to static clock fanout; no frequency translation or spread spectrum	Choose only for simple clock distribution where frequency flexibility and jitter headroom are not required

Compared with Si5332A-D06121-GM, SI5338N-B06121-GMR offers smaller footprint and lower cost but trades off ~0.35 ps RMS jitter and crystal integration; versus ICS853S01AGI-01LFT, it delivers full programmability and multi-standard compliance at the expense of higher design complexity.

Availability

SI5338N-B06121-GMR is available at Aetrix Electronics and suitable for PCIe switch timing, Ethernet switching, and FPGA processor clocking requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for SI5338N-B06121-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5338 product line delivers programmable, low-jitter clock generation for high-speed serial interfaces including PCIe, Ethernet, Fibre Channel, and broadcast video, targeting applications where precision timing, flexibility, and small form factor are critical.

FAQ

What is the primary function of the SI5338N-B06121-GMR?

The SI5338N-B06121-GMR is an I²C-programmable quad clock generator that synthesizes four independent, low-jitter output frequencies from a single input reference. Its core function is replacing multiple fixed-frequency crystal oscillators in high-speed digital systems while enabling dynamic frequency tuning, spread-spectrum control, and mixed-voltage clock distribution - all within a compact 4 × 4 mm QFN package.

Does the SI5338N-B06121-GMR support PCIe Gen 4 timing requirements?

Yes, the SI5338N-B06121-GMR meets PCIe Gen 4 Common Clock jitter specifications with ≤0.45 ps RMS (12 kHz–20 MHz) when configured per Skyworks' recommended settings (PLL bandwidth 2–4 MHz, CDR = 10 MHz). This compliance is verified per PCI-Express Base Specification 4.0 rev. 0.5 and confirmed using the Skyworks PCIe Clock Jitter Tool.

Can the SI5338N-B06121-GMR generate different output formats simultaneously?

Yes, the SI5338N-B06121-GMR supports simultaneous LVPECL, LVDS, HCSL, CMOS, SSTL, and HSTL outputs across its four drivers. Each output pair (CLK0A/B through CLK3A/B) is independently configurable for signal format, voltage level (1.5/1.8/2.5/3.3 V), and termination - enabling direct interfacing with heterogeneous FPGA banks, ASIC I/Os, and PHYs without external level shifters.

What is the minimum and maximum output frequency supported by the SI5338N-B06121-GMR?

The SI5338N-B06121-GMR supports output frequencies from 0.16 MHz to 710 MHz depending on format: LVPECL/LVDS/CML up to 710 MHz, HCSL up to 250 MHz, CMOS up to 200 MHz, and SSTL/HSTL up to 350 MHz. Frequencies above 350 MHz are limited to two unique values simultaneously (Fvco/4 and Fvco/6) due to VCO architecture constraints.

How is the SI5338N-B06121-GMR programmed and configured?

The SI5338N-B06121-GMR is programmed via its I²C/SMBus-compatible interface (SCL/SDA pins) using Skyworks' ClockBuilder Pro software. Configuration includes output frequencies, formats, voltages, spread-spectrum parameters, and alarm thresholds. Factory-programmed OTP NVM retains settings across power cycles, and field updates are supported without hardware changes.

SI5338N-B06121-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338N-B06121-GMR FAQ

1.How can I place an order for SI5338N-B06121-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338N-B06121-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338N-B06121-GMR reliable?

The price and inventory of SI5338N-B06121-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338N-B06121-GMR is usually 5 days.

3.What payment methods are accepted for SI5338N-B06121-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338N-B06121-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338N-B06121-GMR?

SI5338N-B06121-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338N-B06121-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338N-B06121-GMR?

For technical support, including SI5338N-B06121-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338N-B06121-GMR requirements.

6.How does Aetrix verify that SI5338N-B06121-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338N-B06121-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338N-B06121-GMR meets industry standards.

7.What is the process for return or replacement of SI5338N-B06121-GMR?

All SI5338N-B06121-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338N-B06121-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338N-B06121-GMR part is unused and in its original packaging.

Return procedure for SI5338N-B06121-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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