Skyworks Solutions Inc. SI5338N-B06122-GM

Overview

SI5338N-B06122-GM from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation from 1.8/2.5/3.3 V core supply in a 4 × 4 mm 24-QFN package. It replaces up to four crystal oscillators in high-speed serial interface timing applications.

For engineers reviewing the SI5338N-B06122-GM datasheet, SI5338N-B06122-GM pinout, SI5338N-B06122-GM application, or SI5338N-B06122-GM equivalent, key selection considerations include output format flexibility (LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL), independent per-output voltage (1.5–3.3 V), any-frequency synthesis capability (0.16–710 MHz), spread-spectrum control, and PCIe Gen 4 jitter compliance.

Technical Context

The SI5338N-B06122-GM implements a two-stage PLL architecture: a high-stability integer-N PLL (Stage 1) locks to one of six input references (crystal, CMOS, SSTL/HSTL, or differential), followed by four independent MultiSynth™ fractional-N synthesizers (Stage 2) generating each output. Each MultiSynth supports integer or fractional mode with <20 ps phase step resolution and 1 ppm frequency increment/decrement.

Output drivers are fully decoupled-each supports independent signal format, supply voltage (VDDO0–VDDO3), enable control, phase offset (±45 ns), and spread-spectrum modulation (0.5–5.0% deviation, 33–63 kHz rate). The device includes loss-of-lock and loss-of-signal alarms, external feedback for zero-delay mode, and I²C/SMBus configuration with OTP NVM storage.

Key Specifications

Pinout & Package

SI5338N-B06122-GM uses a 24-lead QFN package (4 × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin assignments follow standard Si5338 top-view layout: IN1/IN2 (differential ref 1), IN3/IN4 (single-ended ref 2/3), IN5/IN6 (differential ref 4/5), CLK0A/CLK0B through CLK3A/CLK3B (four differential output pairs), VDDO0–VDDO3 (independent output buffer supplies), VDD (core supply), SCL/SDA (I²C interface), INTR (interrupt output), and RSVD_GND (reserved ground).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Compared with Si5332A-D06122-GM, SI5338N-B06122-GM offers field-upgradable frequency plans and external crystal tuning; compared with ICS854S01IAGLF, it provides full programmability, PCIe Gen 4 compliance, and 60% lower jitter-making it essential for adaptive, high-performance timing systems.

Availability

SI5338N-B06122-GM is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, multi-rate Ethernet switching, and broadcast video synchronization requiring stable component supply across industrial temperature ranges and long production lifecycles.

Supply support for SI5338N-B06122-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and precision analog ICs for infrastructure, automotive, and mobile markets.

The Si5338 product line was designed specifically for high-density, multi-protocol timing consolidation in networking, computing, and communications equipment-enabling replacement of multiple discrete oscillators with a single programmable, low-jitter clock source.

FAQ

What is the maximum differential output frequency supported by the SI5338N-B06122-GM?

The SI5338N-B06122-GM supports differential output frequencies up to 710 MHz for LVPECL and LVDS formats, 473.33 MHz for CML, and 250 MHz for HCSL. These limits are defined by the MultiSynth™ architecture and verified in Table 6 of the official datasheet. Operation above 350 MHz requires use of Fvco/4 or Fvco/6 synthesis paths, limiting simultaneous high-frequency outputs to two unique frequencies.

Does the SI5338N-B06122-GM support PCIe Gen 4 Separate Reference No Spread (SRNS) mode?

Yes, the SI5338N-B06122-GM is explicitly compliant with PCIe Gen 3 SRNS and Gen 4 Common Clock specifications. Its measured 0.11–0.32 ps RMS jitter (10 kHz–50 MHz) in SRNS mode meets PCI-SIG requirements when configured with PLL bandwidth of 2–5 MHz and CDR = 10 MHz, as validated using the Skyworks PCIe Clock Jitter Tool.

Can the SI5338N-B06122-GM generate four different output voltages simultaneously?

Yes-the SI5338N-B06122-GM provides four independent output buffer supplies (VDDO0–VDDO3), each configurable for 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This allows simultaneous generation of, for example, 3.3 V CMOS for a microcontroller, 2.5 V LVDS for an FPGA transceiver, 1.8 V HCSL for a PCIe slot, and 1.5 V SSTL for memory interface-all from a single SI5338N-B06122-GM device.

How is the SI5338N-B06122-GM programmed, and is external nonvolatile memory required?

The SI5338N-B06122-GM is programmed via its I²C/SMBus interface using ClockBuilder Pro software. Configuration is stored in on-chip one-time-programmable (OTP) NVM, eliminating need for external EEPROM. Factory pre-programmed units ship with default settings; field updates are supported via I²C without requiring power cycle or reset.

What is the thermal performance of the SI5338N-B06122-GM in continuous operation?

The SI5338N-B06122-GM has a junction-to-ambient thermal resistance (θJA) of 37 °C/W under still-air conditions. At maximum rated core current (60 mA @ 3.3 V) and worst-case ambient (85 °C), junction temperature remains below 125 °C-well within the 150 °C absolute maximum rating-provided the exposed thermal pad is soldered to a minimum 100 mm² copper pour per datasheet layout guidelines.