Skyworks Solutions Inc. SI5338N-B06122-GMR
- Part No.:
- SI5338N-B06122-GMR
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Application Specific Clock/Timing
- Package:
- 24-VFQFN Exposed Pad
- Datasheet:
-
SI5338N-B06122-GMR.pdf
- Description:
- I2C CONTROL, 4-OUTPUT, ANY FREQU
- Quantity:
- Payment:

- Shipping:

Inventory:4,476
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SI5338N-B06122-GMR from Skyworks Solutions is an I²C-programmable quad clock generator IC with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation from 1.8/2.5/3.3 V core supply in a 4 × 4 mm 24-QFN package. It replaces up to four crystal oscillators in high-speed serial interface timing applications.
For engineers reviewing the SI5338N-B06122-GMR datasheet, SI5338N-B06122-GMR pinout, SI5338N-B06122-GMR application, or SI5338N-B06122-GMR equivalent, key selection criteria include PCIe Gen 4 jitter compliance (0.15–0.45 ps RMS), independent output voltage per driver (1.5/1.8/2.5/3.3 V), MultiSynth™ any-frequency synthesis (0.16–710 MHz), and I²C/SMBus programmability with ClockBuilder Pro support.
Technical Context
The SI5338N-B06122-GMR implements a two-stage PLL architecture: a high-stability reference stage followed by four independent MultiSynth™ fractional-N synthesizers, each driving one output pair. Each synthesizer supports integer or fractional mode with 1 ppb frequency resolution and <20 ps programmable phase step accuracy.
It accepts flexible input references-including 8–30 MHz crystals, 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL, and 5–710 MHz differential clocks-and provides loss-of-lock and loss-of-signal alarms. Output drivers support LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats with independent VDDO per channel and spread-spectrum modulation (0.5–5.0% spread, 33–63 kHz rate).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Phase Jitter (RMS) | 0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 4 common clock jitter spec (≤0.45 ps RMS) |
| Output Frequency Range | 0.16–710 MHz per output; supports up to two >350 MHz frequencies simultaneously (Fvco/4 & Fvco/6) |
| Input Reference Support | Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz) |
| Output Formats | LVPECL, LVDS, HCSL, CML, CMOS, SSTL, HSTL - each output independently configurable |
| Supply Voltages | Core: 1.8/2.5/3.3 V ±10%; Output buffers: 1.4–3.63 V per VDDOx rail |
| Package | 24-pin QFN, 4 × 4 mm, 0.5 mm pitch, exposed thermal pad |
| Operating Temp | –40 °C to +85 °C ambient; suitable for industrial and telecom line card environments |
Pinout & Package
SI5338N-B06122-GMR is housed in a 24-lead QFN package (4 × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin assignments are fixed across Si5338 family variants per Skyworks Rev. 1.6 datasheet Figure 1 (Top View).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN1, IN2, IN5, IN6 | Differential input pairs | Accept 5–710 MHz AC-coupled differential clocks; require external 100 Ω termination |
| IN3, IN4 | Single-ended inputs | Support 5–200 MHz CMOS; VIH = 0.7×VDD, VIL = 0.3×VDD |
| CLK0A/CLK0B – CLK3A/CLK3B | Differential output pairs | Four independent output channels; each configurable for LVPECL/LVDS/HCSL/CML |
| VDDO0–VDDO3 | Output buffer supplies | Independent 1.4–3.63 V rails per output bank; enable mixed-voltage system interfacing |
| SCL, SDA, INTR | I²C interface & interrupt | Standard SMBus-compatible 3.3 V tolerant interface; INTR asserts on LOS/LOL events |
| VDD | Core supply | 1.8/2.5/3.3 V ±10%; PSRR optimized for low-noise clock generation |
| GND, RSVD_GND | Ground connections | Multiple GND pins and reserved ground pad ensure low-impedance return path and thermal dissipation |
Key Features
| Feature | Design Value |
|---|---|
| MultiSynth™ Any-Frequency Synthesis | Four independent outputs each generate any frequency from 0.16–710 MHz with true zero ppm accuracy |
| PCIe Gen 4 Compliance | Meets PCIe Gen 4 Common Clock jitter spec (0.15–0.45 ps RMS) without external filtering |
| Independent Output Voltage Control | Each of four VDDO rails configurable from 1.5 V to 3.3 V, enabling direct interface to mixed-voltage FPGAs and ASICs |
| Glitchless Frequency Adjustment | 1 ppm step size via PINC/FDEC pins; update time ≤667 ns for outputs >18 MHz |
| Programmable Spread Spectrum | Configurable on any output: 0.5–5.0% spread, 33–63 kHz modulation rate, reducing EMI in dense PCB layouts |
| External Feedback Mode | Enables zero-delay clock distribution when used with external feedback path and loop filter |
Applications
| PCIe Gen 4 Switch Timing | Ethernet Switch/Routing |
|---|---|
Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe Gen 4 switch ICs in a 1U server backplane. IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent, low-jitter PCIe-compliant clocks with matched skew and programmable phase alignment. Use Value: Eliminates need for four discrete oscillators; reduces board area by 65% and ensures Gen 4 jitter compliance (≤0.45 ps RMS) across all lanes. | Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10 GbE PHYs, packet processors, and SerDes in a Layer 3 switch. IC Role / Device Role / Timing Role: Flexible frequency translator and buffer supporting mixed-rate Ethernet interfaces with independent output format control. Use Value: Single device replaces multiple oscillators and level translators; supports both LVDS and HCSL outputs at full data rates without external components. |
| Broadcast Video Timing | FPGA Processor Clocking |
Use Scenario: Delivering SMPTE ST 2082 (27 Gbps) pixel clock and auxiliary timing signals (e.g., 148.5 MHz, 74.25 MHz) to video encoder/decoder ASICs in 4K/8K broadcast equipment. IC Role / Device Role / Timing Role: High-precision quad clock source with sub-20 ps phase step resolution for frame-synchronized multi-channel video processing. Use Value: Enables precise inter-channel phase alignment critical for multi-link video transport; jitter <0.7 ps RMS preserves signal integrity at 27 Gbps. | Use Scenario: Supplying core logic, DDR4 memory, transceiver, and debug clocks to Xilinx Versal or Intel Agilex FPGA platforms requiring multiple non-integer-related frequencies. IC Role / Device Role / Timing Role: Configurable clock generator with independent VDDO rails and CMOS/LVDS/HCSL outputs matching diverse FPGA I/O standards. Use Value: Reduces BOM count by consolidating six+ clocks into one IC; eliminates external level shifters and simplifies power sequencing. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad clock generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5338A-B06122-GM | Same silicon, different factory programming; lacks pre-programmed configuration stored in OTP NVM | Requires full I²C initialization at boot; no default output on power-up | Select when full runtime reconfiguration is required and system firmware handles clock setup |
| ICS853S01AGI-01LFT | Fixed-frequency, non-programmable quad LVDS generator; 0.9 ps RMS jitter; no I²C interface | Limited to pre-defined frequencies; no spread spectrum or phase adjustment | Select only for cost-sensitive, static-clock applications where flexibility is not needed |
Compared with Si5338A-B06122-GM, SI5338N-B06122-GMR offers factory-programmed startup configuration for immediate clock output, while ICS853S01AGI-01LFT trades programmability for lower unit cost and simpler integration in fixed-frequency systems.
Availability
SI5338N-B06122-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, Ethernet switching/routing, and broadcast video timing requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.
Supply support for SI5338N-B06122-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.
The Si5338 product line delivers high-performance, software-programmable clock generation for applications demanding ultra-low jitter, multi-format outputs, and flexible frequency synthesis - particularly in high-speed serial interfaces like PCIe, Ethernet, and Fibre Channel.
FAQ
What is the factory-programmed configuration of SI5338N-B06122-GMR?
The SI5338N-B06122-GMR is pre-programmed with a specific clock configuration stored in one-time-programmable (OTP) NVM. Upon power-up, it immediately generates four predefined output frequencies and formats without requiring I²C initialization. This differs from the 'A' variant (e.g., Si5338A-B06122-GM), which boots with no active outputs until configured via I²C. The exact factory settings for SI5338N-B06122-GMR are documented in Skyworks' ordering information guide and can be verified using ClockBuilder Pro software.
Does SI5338N-B06122-GMR support PCIe Gen 4 Separate Reference No Spread (SRNS) mode?
Yes, SI5338N-B06122-GMR supports PCIe Gen 4 SRNS mode with 0.11–0.32 ps RMS jitter (typical) when configured with a PLL bandwidth of 2–4 MHz or 2–5 MHz and CDR set to 10 MHz. This compliance is explicitly verified in Skyworks' Table 12 and confirmed in AN562 application note. The device achieves this using its MultiSynth™ architecture with optimized loop filter settings and low-noise VCO design - no external components are required to meet Gen 4 SRNS requirements.
Can SI5338N-B06122-GMR generate two outputs above 350 MHz simultaneously?
Yes, SI5338N-B06122-GMR can generate two unique frequencies above 350 MHz simultaneously - specifically Fvco/4 and Fvco/6 - as stated in Skyworks' Table 6 Note 6. For example, with Fvco = 2.8 GHz, it can output 700 MHz (Fvco/4) and 466.67 MHz (Fvco/6). Outputs above 350 MHz must use LVPECL, LVDS, or CML formats; HCSL is limited to ≤250 MHz. This capability enables dual high-speed SerDes lane timing in applications like 28 Gbps CEI or 56 Gbps PAM4 interfaces.
What is the maximum output current per VDDO rail on SI5338N-B06122-GMR?
Maximum output current per VDDO rail depends on output format and frequency: LVPECL at 710 MHz draws up to 30 mA, LVDS at 710 MHz draws up to 8 mA, HCSL at 250 MHz draws up to 20 mA, and CMOS at 200 MHz draws 13–18 mA (depending on VDDO voltage). These values are specified in Skyworks' Table 3 and define the minimum decoupling and PCB trace width requirements. Exceeding these limits risks output waveform degradation and increased jitter, especially at high frequencies.
How does the external feedback mode function on SI5338N-B06122-GMR?
External feedback mode on SI5338N-B06122-GMR routes a selected output (e.g., CLK0A) back to the FBK pin, closing the PLL loop externally. This enables zero-delay clock distribution - where the output phase aligns precisely with the input reference - by compensating for propagation delay in the feedback path. The mode requires external passive loop filter components (R/C network) per Skyworks' Figure 27 and is configured via register 0x09[7]. It is commonly used in clock tree fanout applications requiring deterministic latency, such as synchronous Ethernet or deterministic networking switches.
SI5338N-B06122-GMR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- MultiSynth™
- Package/Case:
- 24-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- PLL:
- -
- Main Purpose:
- -
- Input:
- -
- Output:
- -
- Number of Circuits:
- -
- Ratio - Input:Output:
- -
- Differential - Input:Output:
- -
- Frequency - Max:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 24-QFN (4x4)
SI5338N-B06122-GMR FAQ
1.How can I place an order for SI5338N-B06122-GMR through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5338N-B06122-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5338N-B06122-GMR reliable?
The price and inventory of SI5338N-B06122-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338N-B06122-GMR is usually 5 days.
3.What payment methods are accepted for SI5338N-B06122-GMR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338N-B06122-GMR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5338N-B06122-GMR?
SI5338N-B06122-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5338N-B06122-GMR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5338N-B06122-GMR?
For technical support, including SI5338N-B06122-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338N-B06122-GMR requirements.
6.How does Aetrix verify that SI5338N-B06122-GMR is sourced from the original manufacturer or authorized distributors?
All SI5338N-B06122-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338N-B06122-GMR meets industry standards.
7.What is the process for return or replacement of SI5338N-B06122-GMR?
All SI5338N-B06122-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338N-B06122-GMR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5338N-B06122-GMR part is unused and in its original packaging.
Return procedure for SI5338N-B06122-GMR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SI5338N-B06122-GMR Tags

-
LMK00334RTVRQ1
Texas Instruments
.jpg)
-
DSC557-0344FI0T
Microchip Technology

-
9FGV0241AKILFT
Renesas

-
9DBL0452CKILFT
Renesas
.jpg)
-
DSC557-0344FL1T
Microchip Technology
-
RC19008AGND#KB0
Renesas
-
RC19008AGND#BB0
Renesas

-
9DB403DGILFT
Renesas

-
9DB233AGILFT
Renesas

-
9DB803DGILFT
Renesas

-
9FGL0851DKILFT
Renesas
-
AB-557-03-HCHC-F-L-C-T
Abracon LLC
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

