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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338N-B06142-GM

Name: SI5338N-B06142-GM
Brand: Skyworks Solutions Inc.
SKU: SI5338N-B06142-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338N-B06142-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338N-B06142-GM.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5338N-B06142-GM from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation across –40 to +85 °C. It replaces up to four crystal oscillators in Ethernet switch/router, PCIe, and FPGA clocking systems.

For engineers reviewing the SI5338N-B06142-GM datasheet, SI5338N-B06142-GM pinout, SI5338N-B06142-GM application, or SI5338N-B06142-GM equivalent, key selection considerations include its MultiSynth™-based any-frequency synthesis (0.16–710 MHz), independent output voltage per driver (1.5/1.8/2.5/3.3 V), flexible input reference support (8–30 MHz crystal, 5–710 MHz differential), and I²C/SMBus programmability.

Technical Context

The SI5338N-B06142-GM implements a two-stage PLL architecture: a high-stability synthesis stage (VCO + MultiSynth dividers) followed by a fully configurable output stage with independent M/N/R dividers per output. Each of the four outputs supports integer or fractional frequency synthesis with <20 ps programmable phase step resolution.

It integrates loss-of-lock and loss-of-signal alarms, independent output enable (OEB), glitchless frequency increment/decrement (1 ppm steps), and spread-spectrum control (0.5–5.0% spread, 33–63 kHz modulation rate) on any output - all managed via I²C interface with ClockBuilder Pro software support.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps typ (12 kHz–20 MHz); meets PCIe Gen 3 SRNS & Gen 4 common clock jitter requirements
Output Frequency Range	0.16–710 MHz; supports LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats per output
Input Reference Support	8–30 MHz crystal, 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL, 5–710 MHz differential
Core Supply Voltage	1.8 V / 2.5 V / 3.3 V ±10%; PSRR optimized for low-noise timing applications
Operating Temperature	–40 to +85 °C; qualified for industrial and telecom line card environments
Package	24-pin QFN, 4 × 4 mm; compatible with standard reflow profiles and high-density PCB layouts
Power Consumption	45 mA typ core current at 100 MHz on all outputs; scalable buffer-mode current down to 12 mA

Pinout & Package

SI5338N-B06142-GM uses a 24-pin, 4 × 4 mm QFN package with exposed thermal pad. Pin assignments are fixed per Skyworks Si5338 family layout and validated for signal integrity and thermal performance.

Pin/Terminal	Circuit Role	Design Meaning
IN1/IN2, IN5/IN6	Differential Input Pairs	Accept 5–710 MHz AC-coupled differential clocks; require external 100 Ω termination
IN3/IN4	Single-Ended Inputs	Support 5–200 MHz CMOS; VIH/VIL referenced to VDD; internal 20 kΩ pull-up/pull-down
CLK0A/CLK0B–CLK3A/CLK3B	Differential Output Pairs	Four independent drivers; each configurable as LVPECL/LVDS/HCSL/CML with selectable VDDOx (1.5–3.3 V)
VDDO0–VDDO3	Output Buffer Supplies	Independent 1.4–3.63 V supplies per output bank; enable mixed-voltage system interfacing
SCL/SDA	I²C Interface	Standard SMBus-compatible serial bus; supports 100/400 kHz modes; no external pull-ups required
INTR	Interrupt Output	Open-drain status flag for loss-of-lock, loss-of-signal, or configuration error events

Key Features

Feature	Design Value
MultiSynth™ Any-Frequency Synthesis	Generates four independent, zero-ppm-accurate output frequencies simultaneously (0.16–710 MHz) without external components
PCIe Gen 1–4 Compliance	Fully satisfies PCIe Gen 3 SRNS and Gen 4 common clock jitter specs (≤0.32 ps RMS) with configurable PLL bandwidth
Independent Output Voltage Control	Each output bank powered by dedicated VDDOx supply (1.5/1.8/2.5/3.3 V), enabling direct interface to mixed-voltage FPGAs and ASICs
Glitchless Frequency Adjustment	Real-time 1 ppm-step frequency increment/decrement via pin or I²C, with sub-ns update latency
Programmable Spread Spectrum	Configurable SSC on any output: 0.5–5.0% spread depth, 33–63 kHz modulation rate, adjustable center/down-spread mode

Applications

Ethernet Switch/Router Timing	PCIe Gen 1–4 Clocking
Use Scenario: Synchronizing multi-port 1 GbE/10 GbE PHYs and packet processors in enterprise switches. IC Role / Device Role / Timing Role: Primary clock source delivering four low-jitter, format-matched clocks (e.g., 125 MHz LVDS, 156.25 MHz HCSL) to MAC, PHY, and switch fabric. Use Value: Eliminates four discrete oscillators; meets IEEE 802.3 jitter limits (<1.2 ps RMS) via 0.7 ps RMS typical phase noise.	Use Scenario: Providing reference clocks to CPU, GPU, and peripheral controllers in server motherboards with PCIe Gen 4 slots. IC Role / Device Role / Timing Role: Common clock generator meeting PCIe Base Spec 4.0 jitter requirements (≤0.45 ps RMS) across all root complex and endpoint devices. Use Value: Enables single-source clock tree with SRNS-compliant outputs, reducing board-level skew and EMI vs. multiple XO solutions.
Processor & FPGA Clocking	Broadcast Video/Audio Timing
Use Scenario: Driving heterogeneous clock domains in Xilinx Versal or Intel Agilex FPGAs with mixed I/O standards. IC Role / Device Role / Timing Role: Configurable quad-output generator supplying 100 MHz LVDS (GT transceivers), 200 MHz CMOS (logic), 300 MHz HCSL (memory), and 500 MHz LVPECL (analog subsystem). Use Value: Reduces BOM count and layout complexity while maintaining <10 ps pk-pk cycle-cycle jitter across all outputs.	Use Scenario: Master timing reference for SMPTE ST 2082 (12G-SDI) and AES67 audio-over-IP equipment. IC Role / Device Role / Timing Role: Ultra-low-jitter source for 74.25 MHz, 148.5 MHz, and 297 MHz video clocks plus 48 kHz/96 kHz audio sample rates. Use Value: Achieves <0.7 ps RMS jitter critical for 12G-SDI eye diagram compliance and AES67 synchronization accuracy.

Ethernet Switch/Router Timing

PCIe Gen 1–4 Clocking

Use Scenario: Synchronizing multi-port 1 GbE/10 GbE PHYs and packet processors in enterprise switches.

IC Role / Device Role / Timing Role: Primary clock source delivering four low-jitter, format-matched clocks (e.g., 125 MHz LVDS, 156.25 MHz HCSL) to MAC, PHY, and switch fabric.

Use Value: Eliminates four discrete oscillators; meets IEEE 802.3 jitter limits (<1.2 ps RMS) via 0.7 ps RMS typical phase noise.

Use Scenario: Providing reference clocks to CPU, GPU, and peripheral controllers in server motherboards with PCIe Gen 4 slots.

IC Role / Device Role / Timing Role: Common clock generator meeting PCIe Base Spec 4.0 jitter requirements (≤0.45 ps RMS) across all root complex and endpoint devices.

Use Value: Enables single-source clock tree with SRNS-compliant outputs, reducing board-level skew and EMI vs. multiple XO solutions.

Processor & FPGA Clocking

Broadcast Video/Audio Timing

Use Scenario: Driving heterogeneous clock domains in Xilinx Versal or Intel Agilex FPGAs with mixed I/O standards.

IC Role / Device Role / Timing Role: Configurable quad-output generator supplying 100 MHz LVDS (GT transceivers), 200 MHz CMOS (logic), 300 MHz HCSL (memory), and 500 MHz LVPECL (analog subsystem).

Use Value: Reduces BOM count and layout complexity while maintaining <10 ps pk-pk cycle-cycle jitter across all outputs.

Use Scenario: Master timing reference for SMPTE ST 2082 (12G-SDI) and AES67 audio-over-IP equipment.

IC Role / Device Role / Timing Role: Ultra-low-jitter source for 74.25 MHz, 148.5 MHz, and 297 MHz video clocks plus 48 kHz/96 kHz audio sample rates.

Use Value: Achieves <0.7 ps RMS jitter critical for 12G-SDI eye diagram compliance and AES67 synchronization accuracy.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5338A-B-GM	Same die, factory-programmed default configuration; lacks pre-loaded B06142 firmware image	Requires full ClockBuilder Pro configuration; no out-of-box PCIe Gen 3 SRNS compliance	Select when custom frequency plans or non-standard startup behavior are needed
LMK04832RHAT	Two PLLs, dual-loop architecture; higher power (120 mA), larger 48-QFN package; supports JESD204B deterministic latency	Targeted at RF/data converter timing; includes jitter cleaner functionality not present in SI5338N-B06142-GM	Select when sub-100 fs integrated jitter or deterministic delay alignment is required

Compared with Si5338A-B-GM, SI5338N-B06142-GM delivers verified PCIe Gen 3 SRNS and Gen 4 common clock compliance out-of-box, while LM K04832RHAT adds jitter cleaning and deterministic latency at the cost of higher power and footprint - making SI5338N-B06142-GM optimal for space-constrained, standards-compliant digital clocking.

Availability

SI5338N-B06142-GM is available at Aetrix Electronics and suitable for Ethernet switch/router, PCIe Gen 4 server platforms, and broadcast video equipment requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.

Supply support for SI5338N-B06142-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for infrastructure, automotive, and mobile markets.

The Si5338 product line delivers programmable, low-jitter clock generation for high-speed serial interfaces including PCIe, Ethernet, and broadcast video - designed to replace multiple discrete oscillators with a single configurable IC.

FAQ

What is the default configuration of the SI5338N-B06142-GM?

The SI5338N-B06142-GM ships with a factory-programmed configuration optimized for PCIe Gen 3 SRNS and Gen 4 common clock compliance, including pre-set PLL bandwidth, output formats (HCSL), and spread-spectrum settings. This eliminates need for initial ClockBuilder Pro programming in standard deployments. The SI5338N-B06142-GM retains full I²C reprogrammability for field adaptation.

Does the SI5338N-B06142-GM support both differential and single-ended outputs simultaneously?

Yes, the SI5338N-B06142-GM supports up to four differential outputs (LVPECL/LVDS/HCSL/CML) or eight single-ended outputs (CMOS/SSTL/HSTL), or any combination thereof - e.g., two LVDS pairs and two CMOS outputs. Each output driver is independently configurable for format, frequency, voltage, and termination, with no shared resource constraints.

What input reference options does the SI5338N-B06142-GM support?

The SI5338N-B06142-GM accepts multiple input references: an 8–30 MHz fundamental-mode crystal on IN1/IN2; 5–200 MHz CMOS on IN3/IN4; or 5–710 MHz differential signals on IN1/IN2 or IN5/IN6. All inputs support automatic loss-of-signal detection with configurable release time (0.01–1 µs), and the device operates in PLL or buffer (bypass) mode depending on configuration.

How is jitter performance validated for the SI5338N-B06142-GM?

Jitter performance of the SI5338N-B06142-GM is validated per industry standards: PCIe Gen 3/4 compliance measured using the Skyworks PCIe Clock Jitter Tool and Intel Clock Jitter Tool v1.6.4; GbE and OC-12 random jitter tested with Agilent 90804 oscilloscope and RJ/DJ separation. Typical 0.7 ps RMS (12 kHz–20 MHz) is guaranteed across –40 to +85 °C with differential outputs and low-noise input clocks.

Can the SI5338N-B06142-GM generate frequencies above 350 MHz on all four outputs?

No - the SI5338N-B06142-GM can simultaneously generate only two unique frequencies above 350 MHz (specifically Fvco/4 and Fvco/6), due to VCO frequency division constraints. Frequencies from 0.16–350 MHz are fully independent per output. For example, CLK0A/CLK0B may run at 710 MHz while CLK1A/CLK1B runs at 500 MHz, but CLK2A/CLK2B and CLK3A/CLK3B must share one of those two high-frequency values or operate ≤350 MHz.

SI5338N-B06142-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tray

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338N-B06142-GM FAQ

1.How can I place an order for SI5338N-B06142-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338N-B06142-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338N-B06142-GM reliable?

The price and inventory of SI5338N-B06142-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338N-B06142-GM is usually 5 days.

3.What payment methods are accepted for SI5338N-B06142-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338N-B06142-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338N-B06142-GM?

SI5338N-B06142-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338N-B06142-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338N-B06142-GM?

For technical support, including SI5338N-B06142-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338N-B06142-GM requirements.

6.How does Aetrix verify that SI5338N-B06142-GM is sourced from the original manufacturer or authorized distributors?

All SI5338N-B06142-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338N-B06142-GM meets industry standards.

7.What is the process for return or replacement of SI5338N-B06142-GM?

All SI5338N-B06142-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338N-B06142-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338N-B06142-GM part is unused and in its original packaging.

Return procedure for SI5338N-B06142-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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