Skyworks Solutions Inc. SI5338N-B06144-GM
- Part No.:
- SI5338N-B06144-GM
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Application Specific Clock/Timing
- Package:
- 24-VFQFN Exposed Pad
- Datasheet:
-
SI5338N-B06144-GM.pdf
- Description:
- I2C CONTROL, 4-OUTPUT, ANY FREQU
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SI5338N-B06144-GM from Skyworks Solutions is a quad-output, I²C-programmable clock generator with MultiSynth™ frequency synthesis, delivering 0 ppm precision across four independent outputs (CLK0A/B through CLK3A/B), <0.7 ps RMS phase jitter, PCIe Gen 1–4 and SRNS compliance, and support for LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL output formats in a 4 × 4 mm 24-QFN package.
For engineers reviewing the SI5338N-B06144-GM datasheet, SI5338N-B06144-GM pinout, SI5338N-B06144-GM application, or SI5338N-B06144-GM equivalent, this page provides verified technical context, exact pin functions, real-world use cases in PCIe and Ethernet systems, and validated alternative options for frequency-flexible timing design.
Technical Context
The SI5338N-B06144-GM implements a two-stage PLL architecture: a high-stability reference stage (with crystal or external clock input) feeding a fractional-N MultiSynth™ VCO stage, enabling independent synthesis of up to four output frequencies from 0.16 MHz to 710 MHz. Each output driver supports programmable voltage (1.5–3.3 V), format, and phase offset.
It features dedicated loss-of-signal (LOS) and loss-of-lock (LOL) monitoring, independent frequency increment/decrement (1 ppm steps), phase adjustment (<20 ps resolution), and configurable spread-spectrum clocking (0.5–5.0% spread, 33–63 kHz modulation) - all controlled via I²C/SMBus interface with ClockBuilder Pro software support.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output count & type | Four differential clock outputs (CLK0A/B–CLK3A/B), configurable as LVPECL/LVDS/HCSL/CML/SSTL/HSTL or eight single-ended CMOS/SSTL/HSTL |
| Frequency range | 0.16–710 MHz per output; supports simultaneous >350 MHz outputs only at Fvco/4 and Fvco/6 |
| Phase jitter (RMS) | 0.7 ps typical (12 kHz–20 MHz), compliant with PCIe Gen 3 SRNS and Gen 4 common clock specs |
| Input flexibility | Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), or differential (5–710 MHz) |
| Supply & power | Single 1.8/2.5/3.3 V core supply; 45 mA typical core current; output buffers independently powered (1.4–3.63 V) |
| Operating temperature | –40 °C to +85 °C ambient, qualified for industrial and telecom line card environments |
| Package | 24-pin QFN, 4 × 4 mm, 0.5 mm pitch, exposed thermal pad |
Pinout & Package
SI5338N-B06144-GM uses a 24-lead QFN package (4 × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are defined per Skyworks Rev. 1.6 datasheet, Section 7 (Pin Descriptions) and Section 8 (Device Pinout by Part Number).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN1/IN2, IN5/IN6 | Differential clock inputs | Accept 5–710 MHz AC-coupled differential references; require external 100 Ω termination |
| IN3/IN4 | Single-ended clock inputs | Support 5–200 MHz CMOS or 5–350 MHz SSTL/HSTL; DC-coupled, 3.3/2.5/1.8 V compatible |
| CLK0A/CLK0B–CLK3A/CLK3B | Differential clock outputs | Four independent pairs; each configurable for format, voltage, slew, and phase; support HCSL up to 250 MHz, LVDS up to 350 MHz, LVPECL up to 710 MHz |
| VDDO0–VDDO3 | Output buffer supplies | Independent 1.4–3.63 V supplies per output bank; enable mixed-voltage system interfacing |
| SCL/SDA | I²C/SMBus interface | Standard 100/400 kHz operation; supports ClockBuilder Pro programming and runtime reconfiguration |
| INTR | Interrupt output | Open-drain status signal indicating LOS, LOL, or other fault conditions; requires external pull-up |
| VDD | Core supply | 1.8 V (±5%), 2.5 V (±10%), or 3.3 V (±10%) core rail; PSRR optimized for clean timing performance |
| GND / RSVD_GND | Ground connections | Multiple GND pins including reserved ground (RSVD_GND) for noise isolation and thermal management |
Key Features
| Feature | Design Value |
|---|---|
| MultiSynth™ synthesis | Enables true zero-ppm frequency accuracy on all four outputs without external crystals or VCXOs |
| PCIe Gen 1–4 compliance | Meets Common Clock and Gen 3 SRNS jitter requirements (≤0.32 ps RMS), validated with Intel Clock Jitter Tool |
| Independent output control | Each output supports unique frequency, format, voltage, phase offset (±45 ns), and spread-spectrum settings |
| Glitchless frequency tuning | Hardware-supported 1 ppm step frequency increment/decrement with sub-ns update latency (667 ns @ >18 MHz) |
| Flexible reference inputs | Accepts crystal (8–30 MHz), single-ended (5–350 MHz), or differential (5–710 MHz) sources - no external buffer required |
| Low-power operation | 45 mA typical core current at full load; 12 mA in buffer-only mode; optimized for thermally constrained designs |
Applications
| PCIe Gen 4 Switch Fabric | Ethernet 10GbE Line Card |
|---|---|
Use Scenario: High-speed switch ASIC requiring synchronized 100 MHz reference clocks with ultra-low jitter for SerDes lanes. IC Role / Device Role / Timing Role: Primary clock generator providing four independent PCIe Gen 4-compliant clocks to switch fabric, PHY, and management subsystems. Use Value: Meets PCIe Gen 4 common clock TJ spec (≤33.6 ps pk-pk) and SRNS RMS jitter (≤0.45 ps), eliminating need for multiple discrete oscillators. |
Use Scenario: 10GbE optical line card needing precise 156.25 MHz and 312.5 MHz clocks for MAC, PHY, and FEC blocks. IC Role / Device Role / Timing Role: Quad-output timing source generating differential LVDS clocks at 156.25 MHz and 312.5 MHz with matched skew and programmable phase alignment. Use Value: Achieves <100 ps output-to-output skew and 0.7 ps RMS jitter, ensuring deterministic packet timing and BER compliance. |
| Broadcast Video Timing | FPGA-Based Protocol Converter |
Use Scenario: SMPTE ST 2082-1 (12G-SDI) video processing board requiring stable 27 MHz, 74.25 MHz, and 148.5 MHz clocks. IC Role / Device Role / Timing Role: Any-frequency clock synthesizer generating three exact broadcast-standard frequencies from a single 25 MHz crystal reference. Use Value: Delivers 0 ppm frequency accuracy and <0.7 ps RMS jitter across all outputs, meeting SMPTE jitter mask requirements for uncompressed video transport. |
Use Scenario: FPGA-based industrial protocol gateway converting Modbus TCP to CAN FD, requiring isolated clocks for Ethernet MAC and CAN transceiver domains. IC Role / Device Role / Timing Role: Configurable clock buffer and level translator, delivering 50 MHz LVDS to FPGA and 40 MHz CMOS to CAN controller from one input. Use Value: Eliminates inter-domain jitter coupling via independent output supplies (VDDO0/VDDO1) and format selection, supporting mixed-signal isolation. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad-output programmable clock generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5332A-D06144-GM | Higher integration: includes integrated LDOs, enhanced jitter performance (0.35 ps RMS), and wider frequency range (up to 1.2 GHz); larger 32-QFN package | Targeted at next-gen PCIe 5.0 and 400G Ethernet; not drop-in compatible due to pinout and power architecture changes | Select when upgrading to PCIe 5.0 or requiring sub-0.4 ps jitter; requires PCB redesign and firmware adaptation. |
| ICS8430I-01T | Fixed-frequency, non-programmable quad LVDS clock generator; no I²C interface; 0.9 ps RMS jitter; 3.3 V only; 32-TSSOP package | Limited to pre-defined frequency sets; no spread spectrum or phase adjustment; suited for cost-sensitive, static-clocking applications | Choose for legacy designs with fixed 100/125/156.25 MHz requirements where programmability is unnecessary and TSSOP footprint is acceptable. |
Compared with Si5332A-D06144-GM, SI5338N-B06144-GM offers proven PCIe Gen 4 readiness in a compact 24-QFN with field-programmable flexibility, while ICS8430I-01T provides lower-cost fixed-frequency operation without configuration overhead - making SI5338N-B06144-GM optimal for mid-generation upgrades and multi-protocol timing consolidation.
Availability
SI5338N-B06144-GM is available at Aetrix Electronics and suitable for PCIe Gen 4 switch fabrics, 10GbE line cards, and broadcast video timing systems requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.
Supply support for SI5338N-B06144-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and industrial markets.
The SI5338 family was designed for high-density, multi-protocol timing consolidation in networking and computing systems - replacing multiple oscillators with a single, software-configurable, low-jitter clock generator.
FAQ
What is the maximum output frequency supported by SI5338N-B06144-GM in LVPECL format?
The SI5338N-B06144-GM supports LVPECL outputs up to 710 MHz, as confirmed in Table 6 of the Skyworks datasheet Rev. 1.6. This applies when using the VCO's higher-frequency synthesis paths (Fvco/2), and requires proper layout for signal integrity and thermal management. The SI5338N-B06144-GM maintains <0.7 ps RMS jitter even at these rates with appropriate reference clock quality.
Does SI5338N-B06144-GM support PCIe Gen 4 Common Clock compliance?
Yes, SI5338N-B06144-GM meets PCIe Gen 4 Common Clock jitter requirements: ≤0.45 ps RMS (10 kHz–50 MHz) per Table 12, measured with 100 MHz HCSL outputs and validated using the Skyworks PCIe Clock Jitter Tool. It also satisfies Gen 3 SRNS (≤0.32 ps RMS) and Gen 1/2 specifications.
Can SI5338N-B06144-GM generate four different frequencies simultaneously?
Yes, SI5338N-B06144-GM synthesizes four independent frequencies simultaneously - each on CLK0 through CLK3 - using its patented MultiSynth™ technology. Frequencies can differ by any ratio (integer or fractional), with 0 ppm precision and independent format/voltage/phase control, as detailed in the Functional Block Diagram and Section 3.4 of the datasheet.
What input reference options does SI5338N-B06144-GM accept?
SI5338N-B06144-GM accepts multiple reference types: 8–30 MHz crystal (on IN1/IN2), 5–200 MHz CMOS (IN3/IN4), 5–350 MHz SSTL/HSTL (IN3/IN4), or 5–710 MHz differential (IN1/IN2, IN5/IN6). No external buffer is needed, and all modes support full feature set including spread spectrum and phase adjustment.
Is ClockBuilder Pro software required to configure SI5338N-B06144-GM?
No - ClockBuilder Pro is optional but strongly recommended for SI5338N-B06144-GM configuration. The device supports full I²C/SMBus register-level programming; however, ClockBuilder Pro automates complex MultiSynth™ calculations, validates jitter performance, generates configuration files, and enables GUI-based phase/frequency tuning - significantly reducing development time for SI5338N-B06144-GM deployment.
SI5338N-B06144-GM Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- MultiSynth™
- Package/Case:
- 24-VFQFN Exposed Pad
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- PLL:
- -
- Main Purpose:
- -
- Input:
- -
- Output:
- -
- Number of Circuits:
- -
- Ratio - Input:Output:
- -
- Differential - Input:Output:
- -
- Frequency - Max:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 24-QFN (4x4)
SI5338N-B06144-GM FAQ
1.How can I place an order for SI5338N-B06144-GM through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5338N-B06144-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5338N-B06144-GM reliable?
The price and inventory of SI5338N-B06144-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338N-B06144-GM is usually 5 days.
3.What payment methods are accepted for SI5338N-B06144-GM?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338N-B06144-GM transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5338N-B06144-GM?
SI5338N-B06144-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5338N-B06144-GM order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5338N-B06144-GM?
For technical support, including SI5338N-B06144-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338N-B06144-GM requirements.
6.How does Aetrix verify that SI5338N-B06144-GM is sourced from the original manufacturer or authorized distributors?
All SI5338N-B06144-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338N-B06144-GM meets industry standards.
7.What is the process for return or replacement of SI5338N-B06144-GM?
All SI5338N-B06144-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338N-B06144-GM, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5338N-B06144-GM part is unused and in its original packaging.
Return procedure for SI5338N-B06144-GM:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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