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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338N-B06144-GMR

Name: SI5338N-B06144-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338N-B06144-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338N-B06144-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338N-B06144-GMR.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

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Product details

Overview

SI5338N-B06144-GMR from Skyworks Solutions is a quad-output, I²C-programmable clock generator with MultiSynth™ frequency synthesis. It delivers four independent, any-frequency outputs (0.16–710 MHz) with 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 and SRNS compliance, and support for LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL signal formats across 1.5–3.3 V output supplies. It replaces up to four crystal oscillators in high-speed serial interface timing applications.

For engineers reviewing the SI5338N-B06144-GMR datasheet, SI5338N-B06144-GMR pinout, SI5338N-B06144-GMR application, or SI5338N-B06144-GMR equivalent, key selection criteria include PCIe Gen 4 SRNS jitter compliance (0.15–0.45 ps RMS), independent per-output voltage configuration (1.5/1.8/2.5/3.3 V), 24-pin 4×4 mm QFN package, and I²C/SMBus programmability with ClockBuilder Pro software support.

Technical Context

The SI5338N-B06144-GMR implements a two-stage PLL architecture: a high-stability reference stage (with crystal or external clock input) followed by four independent MultiSynth™ fractional-N synthesis paths. Each path supports integer or fractional mode operation, enabling true zero-ppm accuracy and glitchless frequency increment/decrement in 1 ppm steps.

Its output stage provides full format and voltage configurability per driver-LVPECL (0.16–710 MHz), LVDS (0.16–350 MHz), HCSL (0.16–250 MHz), CMOS (0.16–200 MHz), SSTL/HSTL (0.16–350 MHz)-with independent 1.5/1.8/2.5/3.3 V VDDO supplies and <20 ps phase step resolution. Spread spectrum control (0.5–5.0% spread, 33–63 kHz modulation) is available on any output.

Key Specifications

Parameter	Value and Actual Design Meaning
Output count	Four independent differential or single-ended outputs (CLK0A/B through CLK3A/B)
Frequency range	0.16–710 MHz per output; supports simultaneous Fvco/4 and Fvco/6 above 350 MHz
Phase jitter (RMS)	0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 4 Common Clock and SRNS requirements
Input flexibility	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz)
Supply voltages	Core: 1.8/2.5/3.3 V; Output buffers: independently configurable 1.5/1.8/2.5/3.3 V
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch, exposed thermal pad
Interface	I²C/SMBus-compatible serial programming (SCL/SDA), with INTR status interrupt pin

Pinout & Package

SI5338N-B06144-GMR is housed in a 24-pin, 4 × 4 mm QFN package with exposed thermal pad (RoHS-compliant, GMR suffix). Pin assignments follow Skyworks' standard Si5338 pinout: dual differential inputs (IN1/IN2, IN5/IN6), single-ended inputs (IN3/IN4), four differential output pairs (CLK0A/B–CLK3A/B), six VDDO supplies (VDDO0–VDDO3), core VDD, SCL/SDA, INTR, and ground/pad connections.

Pin/Terminal	Circuit Role	Design Meaning
IN1/IN2, IN5/IN6	Differential clock inputs	Accept 5–710 MHz AC-coupled differential clocks; require external 100 Ω termination
IN3/IN4	Single-ended clock inputs	Support 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL; DC-coupled with internal bias
CLK0A/B–CLK3A/B	Differential clock outputs	Four independent pairs; each configurable as LVPECL/LVDS/HCSL/CML with dedicated VDDO
VDDO0–VDDO3	Output buffer supplies	Independent 1.5/1.8/2.5/3.3 V rails per output pair; enable mixed-voltage system interfacing
SCL/SDA	I²C programming interface	Standard SMBus-compatible 2-wire bus; supports ClockBuilder Pro configuration
INTR	Interrupt output	Open-drain status pin indicating loss-of-lock or loss-of-signal events

Key Features

Feature	Design Value
MultiSynth™ synthesis	Enables independent, any-frequency generation on all four outputs with zero ppm error and <20 ps phase step resolution
PCIe Gen 4 compliance	Meets SRNS jitter spec (0.11–0.32 ps RMS) and Common Clock jitter (0.15–0.45 ps RMS) without external filtering
Flexible output configuration	Each output supports format (LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL), voltage (1.5–3.3 V), and slew rate tuning individually
Glitchless frequency tuning	Hardware-supported frequency increment/decrement via PINC/FDEC pins in 1 ppm steps, no output interruption
Spread spectrum control	Per-output SSC with user-selectable spread (0.5–5.0%), modulation rate (33–63 kHz), and direction (up/down/center)

Applications

PCIe Gen 4 Switch Timing	Ethernet Switch/Routing
Use Scenario: Providing synchronized, low-jitter reference clocks to multiple PCIe Gen 4 switch ASICs and endpoint devices in a 1U server chassis. IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent 100 MHz HCSL clocks with SRNS-compliant jitter (<0.32 ps RMS) and matched skew (<100 ps). Use Value: Eliminates need for four discrete oscillators; enables deterministic timing closure and reduces board area by >60% versus discrete solution.	Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10 GbE PHYs, packet processors, and SerDes interfaces in a Layer 3 switch. IC Role / Device Role / Timing Role: Any-frequency synthesizer producing precise Ethernet harmonics from a single 25 MHz crystal reference. Use Value: Achieves sub-1 ps RMS jitter on all outputs, meeting IEEE 802.3bj/802.3by jitter budgets without external clean-up PLLs.
Broadcast Video Timing	FPGA/Processor Clocking
Use Scenario: Delivering frame-synchronized 74.25 MHz (HD), 148.5 MHz (3G-SDI), and 297 MHz (12G-SDI) clocks to video encoder/decoder FPGAs and serializer ICs. IC Role / Device Role / Timing Role: Multi-format clock generator supporting LVDS and HCSL outputs at varying voltages (1.8 V/2.5 V) from one device. Use Value: Enables single-board video infrastructure with zero ppm inter-output frequency error and <45 ns programmable phase offset for pixel alignment.	Use Scenario: Supplying core, memory, and I/O clocks to Xilinx Versal or Intel Agilex FPGAs alongside ARM-based SoCs in industrial edge compute modules. IC Role / Device Role / Timing Role: Configurable buffer and level translator generating 100 MHz DDR4, 200 MHz PCIe, and 500 MHz logic clocks from one 25 MHz reference. Use Value: Reduces BOM count by replacing three separate clock ICs; supports dynamic voltage scaling via independent VDDO rails.

PCIe Gen 4 Switch Timing

Ethernet Switch/Routing

Use Scenario: Providing synchronized, low-jitter reference clocks to multiple PCIe Gen 4 switch ASICs and endpoint devices in a 1U server chassis.

IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent 100 MHz HCSL clocks with SRNS-compliant jitter (<0.32 ps RMS) and matched skew (<100 ps).

Use Value: Eliminates need for four discrete oscillators; enables deterministic timing closure and reduces board area by >60% versus discrete solution.

Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10 GbE PHYs, packet processors, and SerDes interfaces in a Layer 3 switch.

IC Role / Device Role / Timing Role: Any-frequency synthesizer producing precise Ethernet harmonics from a single 25 MHz crystal reference.

Use Value: Achieves sub-1 ps RMS jitter on all outputs, meeting IEEE 802.3bj/802.3by jitter budgets without external clean-up PLLs.

Broadcast Video Timing

FPGA/Processor Clocking

Use Scenario: Delivering frame-synchronized 74.25 MHz (HD), 148.5 MHz (3G-SDI), and 297 MHz (12G-SDI) clocks to video encoder/decoder FPGAs and serializer ICs.

IC Role / Device Role / Timing Role: Multi-format clock generator supporting LVDS and HCSL outputs at varying voltages (1.8 V/2.5 V) from one device.

Use Value: Enables single-board video infrastructure with zero ppm inter-output frequency error and <45 ns programmable phase offset for pixel alignment.

Use Scenario: Supplying core, memory, and I/O clocks to Xilinx Versal or Intel Agilex FPGAs alongside ARM-based SoCs in industrial edge compute modules.

IC Role / Device Role / Timing Role: Configurable buffer and level translator generating 100 MHz DDR4, 200 MHz PCIe, and 500 MHz logic clocks from one 25 MHz reference.

Use Value: Reduces BOM count by replacing three separate clock ICs; supports dynamic voltage scaling via independent VDDO rails.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output programmable clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5338A-B06144-GM	Same die, identical electrical specs; differs only in factory-programmed NVM configuration (B06144 vs. A06144 variant)	Pre-programmed for same default frequencies and output formats; functionally interchangeable in most designs	Select when pre-configured startup behavior matches legacy design requirements without reprogramming
LMK04832ISQE/NOPB	Two PLLs + eight outputs; higher power (120 mA typ), larger 48-QFN package; supports JESD204B deterministic latency	Targeted at RF/data converter timing; lacks PCIe Gen 4 SRNS certification and per-output voltage flexibility	Choose for multi-PLL synchronization or JESD204B systems where deterministic delay matters more than size or PCIe compliance

Compared with Si5338A-B06144-GM, SI5338N-B06144-GMR offers identical performance but with updated factory firmware; versus LMK04832ISQE/NOPB, it trades output count and JESD204B support for smaller footprint, lower power, and certified PCIe Gen 4 timing compliance.

Availability

SI5338N-B06144-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, 10GbE routing infrastructure, and broadcast video synchronization requiring stable component supply, long-term lifecycle assurance, and RoHS-compliant packaging.

Supply support for SI5338N-B06144-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5338 product line was designed as a highly flexible, low-jitter clock generator family for high-speed serial interface timing-including PCIe, Ethernet, Fibre Channel, and broadcast video-where multi-output frequency agility and strict jitter compliance are critical.

FAQ

What is the primary function of the SI5338N-B06144-GMR in a PCIe Gen 4 system?

The SI5338N-B06144-GMR serves as a quad-output clock generator delivering four independent, low-jitter reference clocks compliant with PCIe Gen 4 Separate Reference No Spread (SRNS) specifications. It produces 100 MHz HCSL clocks with ≤0.32 ps RMS jitter (typical), enabling timing closure for switches and endpoints without external jitter cleaners. Its MultiSynth™ engine ensures zero ppm frequency accuracy across all outputs, critical for deterministic link training.

Does the SI5338N-B06144-GMR support both differential and single-ended output formats simultaneously?

Yes, the SI5338N-B06144-GMR supports mixed-mode output configurations: any combination of differential (LVPECL/LVDS/HCSL/CML) and single-ended (CMOS/SSTL/HSTL) signals across its four output drivers. Each output pair (CLK0A/B–CLK3A/B) can be independently assigned format and voltage (1.5/1.8/2.5/3.3 V), allowing direct interfacing with diverse FPGA I/O banks, ASIC clock inputs, and memory controllers without level-shifting components.

How is the SI5338N-B06144-GMR programmed, and what tools are required?

The SI5338N-B06144-GMR is programmed via its I²C/SMBus interface using Skyworks' ClockBuilder Pro software. This GUI tool enables full configuration of output frequencies, formats, voltages, spread spectrum, phase offsets, and alarm thresholds. Configuration can be stored in on-chip OTP memory for autonomous startup. No external programmer is needed-standard I²C host controller or evaluation board suffices for development and production programming of SI5338N-B06144-GMR.

What is the maximum output frequency supported by the SI5338N-B06144-GMR, and under what conditions?

The SI5338N-B06144-GMR supports up to 710 MHz on LVPECL outputs and 350 MHz on LVDS/HCSL/SSTL/HSTL outputs. For frequencies above 350 MHz, only two unique outputs may operate simultaneously-at Fvco/4 and Fvco/6-due to VCO frequency constraints. All outputs maintain 0.7 ps RMS typical phase jitter when driven with low-noise differential references and proper layout per Skyworks AN360 guidelines.

Is the SI5338N-B06144-GMR pin-compatible with other Si5338 variants such as the Si5338A or Si5338B?

Yes, all Si5338 variants-including SI5338N-B06144-GMR, Si5338A-B06144-GM, and Si5338B-D06144-GM-are mechanically and electrically pin-compatible in the 24-pin QFN package. Differences lie solely in factory-programmed OTP content (default configuration, frequency plans, and feature enables), not in pin function or timing behavior. PCBs designed for one Si5338 variant can accept any other without modification.

SI5338N-B06144-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338N-B06144-GMR FAQ

1.How can I place an order for SI5338N-B06144-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338N-B06144-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338N-B06144-GMR reliable?

The price and inventory of SI5338N-B06144-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338N-B06144-GMR is usually 5 days.

3.What payment methods are accepted for SI5338N-B06144-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338N-B06144-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338N-B06144-GMR?

SI5338N-B06144-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338N-B06144-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338N-B06144-GMR?

For technical support, including SI5338N-B06144-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338N-B06144-GMR requirements.

6.How does Aetrix verify that SI5338N-B06144-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338N-B06144-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338N-B06144-GMR meets industry standards.

7.What is the process for return or replacement of SI5338N-B06144-GMR?

All SI5338N-B06144-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338N-B06144-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338N-B06144-GMR part is unused and in its original packaging.

Return procedure for SI5338N-B06144-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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