Skyworks Solutions Inc. SI5338N-B06153-GMR

Overview

SI5338N-B06153-GMR from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation across –40 to +85 °C. It replaces up to four crystal oscillators in high-speed serial interface timing applications including PCIe root complexes and FPGA-based compute platforms.

For engineers reviewing the SI5338N-B06153-GMR datasheet, SI5338N-B06153-GMR pinout, SI5338N-B06153-GMR application, or SI5338N-B06153-GMR equivalent, key selection criteria include its MultiSynth™-based any-frequency synthesis (0.16–710 MHz per output), independent output voltage support (1.5/1.8/2.5/3.3 V), spread-spectrum capability (0.5–5.0% down-spread), and 24-QFN package compatibility with space-constrained PCB layouts.

Technical Context

The SI5338N-B06153-GMR implements a two-stage PLL architecture: a high-stability input stage with programmable R-divider and a fractional-N MultiSynth™ synthesis stage per output, enabling independent frequency generation with <1 ppb resolution. Its output stage supports mixed-signal formats-LVPECL, LVDS, HCSL, CMOS, SSTL, HSTL-each with dedicated VDDO supply and configurable slew rate.

It accepts multiple reference inputs: 8–30 MHz crystal, 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL, or 5–710 MHz differential; all routed through a flexible input multiplexer. Loss-of-signal and loss-of-lock monitoring, independent phase/frequency increment/decrement (20 ps / 1 ppm steps), and external feedback mode for zero-delay operation are integrated at silicon level.

Key Specifications

Pinout & Package

SI5338N-B06153-GMR is housed in a 24-lead QFN package (4 × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin assignments follow Skyworks' standardized Si5338 pinout: dual differential inputs (IN1/IN2, IN5/IN6), two single-ended inputs (IN3, IN4), four differential output pairs (CLK0A/B through CLK3A/B), six VDDO rails (VDDO0–VDDO3 plus VDDO1/VDDO2), core VDD, SCL/SDA, INTR, and reserved ground.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Compared with SI5338N-B06153-GMR, the Si5332A offers higher channel count and lower jitter but increases BOM complexity and cost, while the ICS8430I-01T sacrifices programmability and EMI control for simplicity and price-making SI5338N-B06153-GMR optimal for dynamically configured, multi-standard timing systems.

Availability

SI5338N-B06153-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 server motherboards, 10/25 GbE switch fabric designs, and FPGA-based broadcast video equipment requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for SI5338N-B06153-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and mobile markets.

The SI5338N-B06153-GMR belongs to Skyworks' Si5338 family of programmable clock generators, designed specifically for high-speed serial interface timing in computing, networking, and telecom systems demanding low jitter, multi-format flexibility, and field-upgradable configuration.

FAQ

What is the maximum output frequency supported by SI5338N-B06153-GMR in LVPECL mode?

The SI5338N-B06153-GMR supports up to 710 MHz in LVPECL output mode when operating within its specified VDDO voltage range (2.5–3.3 V) and thermal limits. This capability enables direct clocking of high-speed SerDes lanes in PCIe Gen 4 and 100G Ethernet applications without external frequency multiplication.

Does SI5338N-B06153-GMR support PCIe Gen 4 Separate Reference No Spread (SRNS) compliance?

Yes, SI5338N-B06153-GMR achieves 0.11–0.32 ps RMS jitter in PCIe Gen 3 SRNS mode and meets PCIe Gen 4 common clock jitter requirements (0.15–0.45 ps RMS) when configured with a 2–5 MHz PLL bandwidth and CDR = 10 MHz, as verified per PCI-SIG specifications and Skyworks AN562 test methodology.

Can SI5338N-B06153-GMR generate different output voltages simultaneously on its four output banks?

Yes, SI5338N-B06153-GMR supports independent VDDO supplies (VDDO0–VDDO3) per output bank, allowing simultaneous 1.8 V LVDS, 2.5 V HCSL, 3.3 V CMOS, and 1.5 V SSTL outputs-enabling direct interfacing with mixed-voltage FPGAs, ASICs, and memory controllers without level-shifting circuitry.

How is spread-spectrum clocking (SSC) configured on SI5338N-B06153-GMR?

SSC is configured per-output via ClockBuilder Pro software or direct I²C register writes to enable down-spread modulation at user-defined rates (33–63 kHz) and depths (0.5–5.0%). The SI5338N-B06153-GMR applies SSC only to the selected output(s), leaving others unaffected-critical for mixed-signal systems requiring both EMI-reduced and clean clocks.

What reference inputs does SI5338N-B06153-GMR accept, and what is the minimum crystal frequency supported?

SI5338N-B06153-GMR accepts 8–30 MHz crystals, 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL, or 5–710 MHz differential references. The minimum supported crystal frequency is 8 MHz, with on-chip load capacitance support of 11–13 pF and recommended external loading of 17–19 pF per AN360 guidelines.