Skyworks Solutions Inc. SI5338N-B06157-GM

Overview

SI5338N-B06157-GM from Skyworks Solutions is a quad-output, I²C-programmable clock generator implementing MultiSynth™ frequency synthesis. It delivers four independent, any-frequency differential or single-ended clocks (up to 710 MHz LVPECL/LVDS, 350 MHz SSTL/HSTL) with 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation across –40 to +85 °C in telecom and high-speed serial applications.

For engineers reviewing the SI5338N-B06157-GM datasheet, SI5338N-B06157-GM pinout, SI5338N-B06157-GM application, or SI5338N-B06157-GM equivalent, key selection considerations include its 24-QFN package, I²C/SMBus programmability, per-output voltage selection (1.5/1.8/2.5/3.3 V), independent phase/frequency adjustment (±45 ns / 1 ppm steps), and spread-spectrum capability (0.5–5.0% down-spread, 33–63 kHz).

Technical Context

The SI5338N-B06157-GM integrates a dual-stage PLL architecture: a high-stability reference stage (with crystal or external clock input) followed by four independent MultiSynth™ fractional-N synthesis blocks. Each output driver supports configurable format (LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL) and supply voltage (VDDOx), enabling mixed-signal timing in heterogeneous systems.

It features loss-of-lock and loss-of-signal monitoring, programmable initial phase offset (±45 ns), glitchless frequency increment/decrement via pin control or I²C, and external feedback mode for zero-delay operation - all managed through on-chip OTP NVM and RAM-based runtime configuration.

Key Specifications

Pinout & Package

SI5338N-B06157-GM uses a 24-lead QFN package (4 mm × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin assignments are fixed per the Si5338 family: IN1/IN2 (diff clk0), IN3/IN4 (SE clk1), IN5/IN6 (diff clk2), CLK0A–CLK3B (four differential output pairs), VDD/VDDOx (core and output supply rails), SCL/SDA/INTR (I²C interface and interrupt), and RSVD_GND (reserved ground).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output programmable clock generator applications.

Compared with Si5332A-D06157-GM, SI5338N-B06157-GM offers broader input flexibility (crystal + multiple external references) and lower cost, while ICS853S01AG-01LF provides simpler qualification but lacks programmability and multi-format support.

Availability

SI5338N-B06157-GM is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, Ethernet switch clocking, and broadcast video sync applications requiring stable component supply, long-term lifecycle assurance, and full traceability.

Supply support for SI5338N-B06157-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5338 product line was designed for high-performance, software-configurable clock generation in multi-protocol, multi-rate systems such as networking switches, broadcast infrastructure, and FPGA-based accelerators.

FAQ

What is the primary function of the SI5338N-B06157-GM in a system?

The SI5338N-B06157-GM serves as a quad-output, I²C-programmable clock generator that synthesizes four independent, any-frequency clocks from a single reference. Its core function is to replace multiple fixed-frequency oscillators or serve as a flexible frequency translator in high-speed digital systems like PCIe switches and Ethernet routers. The SI5338N-B06157-GM achieves this using Skyworks' patented MultiSynth™ technology, enabling precise zero-ppm frequency accuracy and low-jitter performance across diverse output formats.

Does the SI5338N-B06157-GM support PCIe Gen 4 timing requirements?

Yes, the SI5338N-B06157-GM meets PCIe Gen 4 Common Clock jitter specifications with ≤0.45 ps RMS (12 kHz–20 MHz) when configured per Skyworks' validated settings. It is explicitly listed as PCIe Gen 1/2/3/4 Common Clock and Gen 3 SRNS compliant in its official documentation. The SI5338N-B06157-GM achieves this using optimized PLL loop bandwidth (2–4 MHz or 2–5 MHz) and CDR-aligned measurement methodology per PCI-SIG standards.

Can the SI5338N-B06157-GM generate both differential and single-ended outputs simultaneously?

Yes, the SI5338N-B06157-GM supports simultaneous differential (LVPECL/LVDS/HCSL/CML) and single-ended (CMOS/SSTL/HSTL) outputs across its four output pairs. Each output driver is independently configurable for format and supply voltage (VDDOx), allowing mixed-mode operation - for example, CLK0A/B as LVDS, CLK1A/B as CMOS, CLK2A/B as HCSL, and CLK3A/B as SSTL - all from one device. This eliminates external level translators in heterogeneous timing architectures.

What is the minimum and maximum input frequency supported by the SI5338N-B06157-GM?

The SI5338N-B06157-GM accepts input frequencies ranging from 5 MHz to 710 MHz depending on interface type: 8–30 MHz for crystal; 5–200 MHz for CMOS; 5–350 MHz for SSTL/HSTL; and 5–710 MHz for differential inputs. In clock buffer (PLL bypass) mode, operation down to 1 MHz is supported, though loss-of-signal detection is disabled below 5 MHz. These ranges are confirmed in Tables 6 and 8–11 of the official Skyworks datasheet Rev. 1.6.

How is the SI5338N-B06157-GM programmed, and what tools are required?

The SI5338N-B06157-GM is programmed via an I²C/SMBus-compatible 2-wire serial interface (SCL/SDA pins) operating up to 400 kHz. Configuration is performed using Skyworks' ClockBuilder Pro software, which generates register maps and .c files for integration into host firmware. The SI5338N-B06157-GM also supports pin-controlled frequency/phase adjustments and stores factory-programmed settings in on-chip OTP memory for autonomous startup.