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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338N-B06173-GMR

Name: SI5338N-B06173-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338N-B06173-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338N-B06173-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338N-B06173-GMR.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

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Product details

Overview

SI5338N-B06173-GMR from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation across –40 to +85 °C. It replaces up to four crystal oscillators in high-speed serial interface timing applications such as PCIe root complexes and FPGA clock trees.

For engineers reviewing the SI5338N-B06173-GMR datasheet, SI5338N-B06173-GMR pinout, SI5338N-B06173-GMR application, or SI5338N-B06173-GMR equivalent, key selection criteria include its MultiSynth™-based any-frequency synthesis (0.16–710 MHz per output), independent output voltage control (1.5/1.8/2.5/3.3 V), spread-spectrum capability (0.5–5.0% down-spread), and 24-QFN package compatibility with space-constrained PCB layouts.

Technical Context

The SI5338N-B06173-GMR implements a two-stage PLL architecture: a high-stability reference PLL (Stage 1) locks to one of six input sources (crystal, CMOS, SSTL/HSTL, or differential), followed by four independent MultiSynth™ fractional-N synthesizers (Stage 2) generating each output with integer or fractional division. Its synthesis resolution is 1 ppb, and it supports external feedback for zero-delay mode.

Each output driver supports LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats with independent supply voltage selection (VDDO0–VDDO3), programmable phase offset (±45 ns, <20 ps step), and glitchless frequency increment/decrement (1 ppm steps). Loss-of-lock and loss-of-signal alarms are provided via the INTR pin.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 3 SRNS and Gen 4 common clock jitter requirements
Output Frequency Range	0.16–710 MHz per channel; supports LVPECL/LVDS up to 710 MHz, HCSL up to 250 MHz, CMOS up to 200 MHz
Input Reference Support	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz)
Supply Voltages	Core: 1.8/2.5/3.3 V ±10%; Output buffers: independently configurable 1.5/1.8/2.5/3.3 V
Package & Pins	24-pin QFN (4 × 4 mm); 4 differential clock outputs (CLK0A/B–CLK3A/B), 6 input pins (IN1–IN6), I²C interface (SCL/SDA), interrupt (INTR)
Temperature Range	–40 to +85 °C ambient; qualified for industrial and telecom line card deployment
Power Consumption	45 mA typical core current at 100 MHz on all outputs and 25 MHz reference clock

Pinout & Package

SI5338N-B06173-GMR is housed in a thermally enhanced 24-lead QFN package (4 mm × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin 1 is top-left corner (IN1), and pin 24 is bottom-right (GND). The package supports reflow soldering per JEDEC J-STD-020 (peak 260 °C).

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2, IN5, IN6	Differential input pairs	Accept AC-coupled differential clocks up to 710 MHz; require external 100 Ω termination
IN3, IN4	Single-ended input pins	Support CMOS/SSTL/HSTL inputs up to 350 MHz; VIH = 0.7×VDD, VIL = 0.3×VDD
CLK0A–CLK3B	Differential output pairs (4 channels)	Configurable per-channel format (LVPECL/LVDS/HCSL/CML) and voltage (1.5–3.3 V)
VDDO0–VDDO3	Independent output buffer supplies	Enable mixed-voltage clock distribution without level shifters
SCL, SDA	I²C/SMBus interface	Supports standard/fast-mode (100/400 kHz); enables full register configuration and status readback
INTR	Open-drain interrupt output	Asserts on loss-of-lock, loss-of-signal, or other fault conditions; requires external pull-up

Key Features

Feature	Design Value
MultiSynth™ synthesis	Four independent, any-frequency outputs (0.16–710 MHz) with true zero-ppm accuracy and 1 ppb resolution
PCIe compliance	Fully compliant with PCIe Gen 1/2/3/4 Common Clock and Gen 3 SRNS jitter specifications
Flexible output configuration	Per-output format selection (LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL) and voltage (1.5/1.8/2.5/3.3 V)
Glitchless frequency tuning	Independent frequency increment/decrement via pin or I²C in 1 ppm steps, update time ≤667 ns
Programmable spread spectrum	Configurable on any output: spread range 0.5–5.0%, modulation rate 33–63 kHz, down-spread only
Status monitoring	Dedicated INTR pin reports loss-of-lock and loss-of-signal events with sub-10 ms detection latency

Applications

PCIe Gen 4 Root Complex Timing	Ethernet Switch Clock Tree
Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe Gen 4 endpoints and switch fabric in a 1U server motherboard. IC Role / Device Role / Timing Role: Quad-output clock generator delivering four low-jitter, phase-aligned clocks with PCIe Gen 4 common clock compliance. Use Value: Eliminates need for four discrete oscillators; reduces board area by >60% and ensures deterministic inter-lane skew <100 ps.	Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1 GbE/10 GbE PHYs and packet processor interfaces in a modular L2/L3 switch. IC Role / Device Role / Timing Role: Programmable frequency translator and buffer supporting mixed-rate Ethernet PHY timing with independent voltage domains. Use Value: Enables single-component support for multi-standard Ethernet timing; simplifies BOM and eliminates external level shifters via per-output VDDO control.
FPGA-Based Broadcast Video System	Telecom Line Card Synchronization
Use Scenario: Delivering precise 74.25 MHz (HD-SDI), 148.5 MHz (3G-SDI), and 297 MHz (12G-SDI) clocks to FPGA-based video processing pipelines and serializer ICs. IC Role / Device Role / Timing Role: Any-frequency clock synthesizer generating SMPTE-compliant video rates with sub-20 ps phase step resolution. Use Value: Achieves frame-accurate synchronization across multiple video standards without custom crystal sets or external dividers.	Use Scenario: Distributing 155.52 MHz (OC-3), 622.08 MHz (OC-12), and 2.488 GHz (OC-48) clocks across DSPs, framer ICs, and SerDes in a carrier-grade optical line card. IC Role / Device Role / Timing Role: High-stability clock generator with OC-12 random jitter ≤0.7 ps RMS and external feedback for zero-delay operation. Use Value: Meets Telcordia GR-1244-CORE jitter requirements while enabling flexible frequency planning across SONET/SDH layers.

PCIe Gen 4 Root Complex Timing

Ethernet Switch Clock Tree

Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe Gen 4 endpoints and switch fabric in a 1U server motherboard.

IC Role / Device Role / Timing Role: Quad-output clock generator delivering four low-jitter, phase-aligned clocks with PCIe Gen 4 common clock compliance.

Use Value: Eliminates need for four discrete oscillators; reduces board area by >60% and ensures deterministic inter-lane skew <100 ps.

Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1 GbE/10 GbE PHYs and packet processor interfaces in a modular L2/L3 switch.

IC Role / Device Role / Timing Role: Programmable frequency translator and buffer supporting mixed-rate Ethernet PHY timing with independent voltage domains.

Use Value: Enables single-component support for multi-standard Ethernet timing; simplifies BOM and eliminates external level shifters via per-output VDDO control.

FPGA-Based Broadcast Video System

Telecom Line Card Synchronization

Use Scenario: Delivering precise 74.25 MHz (HD-SDI), 148.5 MHz (3G-SDI), and 297 MHz (12G-SDI) clocks to FPGA-based video processing pipelines and serializer ICs.

IC Role / Device Role / Timing Role: Any-frequency clock synthesizer generating SMPTE-compliant video rates with sub-20 ps phase step resolution.

Use Value: Achieves frame-accurate synchronization across multiple video standards without custom crystal sets or external dividers.

Use Scenario: Distributing 155.52 MHz (OC-3), 622.08 MHz (OC-12), and 2.488 GHz (OC-48) clocks across DSPs, framer ICs, and SerDes in a carrier-grade optical line card.

IC Role / Device Role / Timing Role: High-stability clock generator with OC-12 random jitter ≤0.7 ps RMS and external feedback for zero-delay operation.

Use Value: Meets Telcordia GR-1244-CORE jitter requirements while enabling flexible frequency planning across SONET/SDH layers.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D06173-GM	Higher integration: 8 outputs, integrated crystal option, lower jitter (0.35 ps RMS), but larger 32-QFN package	Targets systems requiring >4 outputs or tighter jitter budgets (e.g., 400G Ethernet, AI accelerators)	Select when needing ≥8 outputs or sub-0.5 ps RMS jitter; not drop-in due to pin count and footprint change
ICS8430I-01T	Fixed-frequency (non-programmable), 4-output LVDS generator; no I²C interface; 1.2 ps RMS jitter	Used in cost-sensitive, static-clocking applications where frequency flexibility is unnecessary	Choose for fixed-rate designs with minimal firmware overhead; lacks any-frequency synthesis and spread-spectrum capability

Compared with Si5332A-D06173-GM and ICS8430I-01T, SI5338N-B06173-GMR uniquely balances programmability, jitter performance, and compact 24-QFN packaging-making it optimal for mid-density FPGA, PCIe, and telecom applications where field reconfiguration and board space are critical constraints.

Availability

SI5338N-B06173-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 timing, Ethernet switch clock trees, and broadcast video systems requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for SI5338N-B06173-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and mobile markets.

The Si5338 family was designed for high-performance, software-configurable clock generation in datacenter, networking, and broadcast equipment-emphasizing low jitter, multi-format outputs, and I²C programmability without external components.

FAQ

What is the primary function of the SI5338N-B06173-GMR in a system design?

The SI5338N-B06173-GMR serves as a programmable quad-output clock generator that synthesizes up to four independent, low-jitter frequencies from a single reference source. It replaces multiple discrete oscillators in applications like PCIe timing and FPGA clock trees, reducing bill-of-materials count and PCB area while enabling dynamic frequency reconfiguration via I²C. Its MultiSynth™ architecture ensures true zero-ppm accuracy across all outputs.

Does the SI5338N-B06173-GMR support PCIe Gen 4 timing requirements?

Yes, the SI5338N-B06173-GMR meets PCIe Gen 4 common clock jitter specifications with 0.15–0.45 ps RMS jitter (10 kHz–50 MHz) under specified test conditions. It is explicitly validated for PCIe Gen 1/2/3/4 Common Clock and Gen 3 SRNS compliance per the Skyworks datasheet Rev. 1.6, using HCSL 100 MHz outputs and Intel Clock Jitter Tool v1.6.4 verification.

Can the SI5338N-B06173-GMR generate different output voltages simultaneously?

Yes, the SI5338N-B06173-GMR supports independent output buffer supply voltages (VDDO0–VDDO3) selectable per channel at 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This allows simultaneous generation of LVDS (2.5 V), HCSL (1.8 V), and CMOS (3.3 V) signals without external level shifters-enabling mixed-voltage clock distribution in heterogeneous SoC/FPGA systems.

How is the SI5338N-B06173-GMR programmed and configured?

The SI5338N-B06173-GMR is programmed via an I²C/SMBus-compatible 2-wire interface (SCL/SDA) operating at up to 400 kHz. Configuration is simplified using Skyworks' ClockBuilder Pro software, which generates register maps and .c files for embedded initialization. All settings-including output format, frequency, phase offset, and spread spectrum-are stored in on-chip OTP memory and auto-load at power-on.

What package type and thermal characteristics does the SI5338N-B06173-GMR have?

The SI5338N-B06173-GMR uses a 24-lead QFN package measuring 4 mm × 4 mm with 0.5 mm pitch and an exposed thermal pad. Its thermal resistance is θJA = 37 °C/W (still air) and θJC = 10 °C/W, enabling reliable operation at full load within the –40 to +85 °C industrial temperature range. The package complies with JEDEC J-STD-020 reflow profiles (peak 260 °C).

SI5338N-B06173-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338N-B06173-GMR FAQ

1.How can I place an order for SI5338N-B06173-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338N-B06173-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338N-B06173-GMR reliable?

The price and inventory of SI5338N-B06173-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338N-B06173-GMR is usually 5 days.

3.What payment methods are accepted for SI5338N-B06173-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338N-B06173-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338N-B06173-GMR?

SI5338N-B06173-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338N-B06173-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338N-B06173-GMR?

For technical support, including SI5338N-B06173-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338N-B06173-GMR requirements.

6.How does Aetrix verify that SI5338N-B06173-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338N-B06173-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338N-B06173-GMR meets industry standards.

7.What is the process for return or replacement of SI5338N-B06173-GMR?

All SI5338N-B06173-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338N-B06173-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338N-B06173-GMR part is unused and in its original packaging.

Return procedure for SI5338N-B06173-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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