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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338N-B06174-GMR

Name: SI5338N-B06174-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338N-B06174-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338N-B06174-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338N-B06174-GMR.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5338N-B06174-GMR from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation across –40 to +85 °C in a 4 × 4 mm 24-QFN package. It replaces up to four crystal oscillators in high-speed serial interface timing applications.

For engineers reviewing the SI5338N-B06174-GMR datasheet, SI5338N-B06174-GMR pinout, SI5338N-B06174-GMR application, or SI5338N-B06174-GMR equivalent, this page delivers verified specifications, validated pin functions, confirmed PCIe/10GbE/Ethernet switch use cases, and two rigorously cross-checked alternative parts for frequency synthesis design review.

Technical Context

The SI5338N-B06174-GMR implements a dual-stage PLL architecture: a high-stability reference PLL (Stage 1) locks to one of six input sources (crystal, CMOS, SSTL/HSTL, or differential), followed by four independent MultiSynth™ fractional-N synthesizers (Stage 2) generating output clocks with true zero-ppm accuracy. Each output driver supports LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats at voltages from 1.5 V to 3.3 V.

It features per-output programmable phase offset (<20 ps step resolution), independent frequency increment/decrement (1 ppm steps), spread-spectrum control (0.5–5.0% spread, 33–63 kHz modulation), loss-of-lock and loss-of-signal alarms, and external feedback mode for zero-delay operation - all configured via I²C/SMBus interface with ClockBuilder Pro software support.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 3 SRNS and Gen 4 common clock jitter requirements.
Output Count & Flexibility	Four independent outputs: up to 4 differential (LVPECL/LVDS/HCSL/CML) or 8 single-ended (CMOS/SSTL/HSTL), or mixed configuration.
Frequency Range	0.16–710 MHz per output; supports PCIe (100 MHz HCSL), 10GbE (156.25 MHz), and broadcast video (27/74.25/148.5 MHz) directly.
Input Reference Support	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz).
Supply & Power	Single 1.8/2.5/3.3 V core supply; 45 mA typical core current; output buffers independently powered (1.4–3.63 V).
Operating Temperature	–40 to +85 °C ambient; qualified for industrial and telecom line card deployment.
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch; RoHS-compliant, halogen-free, MSL3.

Pinout & Package

SI5338N-B06174-GMR is housed in a 24-lead QFN package (4 × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are validated per Skyworks Rev. 1.6 datasheet Figure 1 (Top View) and Section 7 "Pin Descriptions".

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2	Differential input pair #1	Accepts 5–710 MHz AC-coupled differential clock; internal 100 Ω termination enabled.
IN3, IN4	Single-ended input pair	Supports CMOS/SSTL/HSTL inputs (5–350 MHz); each pin configurable as independent reference source.
IN5, IN6	Differential input pair #2	Second 5–710 MHz differential input path; enables multi-reference redundancy or frequency translation.
CLK0A, CLK0B to CLK3A, CLK3B	Differential output pairs	Four fully independent LVPECL/LVDS/HCSL/CML outputs; each with dedicated VDDOx supply and format selection.
VDDO0–VDDO3	Output buffer supplies	Independent 1.4–3.63 V supplies per output bank; enables mixed-voltage system interfacing (e.g., 1.8 V FPGA + 3.3 V PHY).
VDD	Core supply	1.8/2.5/3.3 V ±10% core power; PSRR optimized for clean clock synthesis under noisy rail conditions.
SCL, SDA	I²C/SMBus interface	Standard 100/400 kHz I²C bus; supports in-system programming and real-time frequency adjustment.
INTR	Interrupt output	Open-drain status flag for loss-of-lock, loss-of-signal, or configuration error; simplifies system-level fault monitoring.
OEB, PINC, FINC	Hardware control pins	Enable/disable outputs (OEB), and perform glitchless frequency/phase increments (PINC/FINC) without I²C transaction overhead.
GND, RSVD_GND	Ground terminals	Multiple GND pins including reserved ground (RSVD_GND) for optimal noise isolation and return path integrity.

Key Features

Feature	Design Value
MultiSynth™ fractional-N synthesis	Enables any-frequency generation (0.16–710 MHz) on each output with true zero-ppm accuracy - no external crystals required per channel.
Per-output voltage & format control	Each of four outputs supports independent selection of LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL and 1.5/1.8/2.5/3.3 V drive level - eliminates level-shifting components.
Glitchless frequency tuning	Hardware-controlled frequency increment/decrement (1 ppm steps) enables dynamic clock rate adaptation in live systems without output interruption.
Programmable phase alignment	±45 ns initial phase offset and <20 ps step resolution per output allow precise inter-channel skew management for SerDes lane deskew.
PCIe Gen 3 SRNS & Gen 4 compliance	Validated 0.11–0.45 ps RMS jitter performance in SRNS and common clock modes satisfies Intel PCIe Base Spec 4.0 requirements.
Spread-spectrum clocking (SSC)	Configurable SSC on any output (0.5–5.0% spread, 33–63 kHz) reduces EMI peak emissions without requiring board-level redesign.

Applications

PCIe Gen 1–4 Switch Timing	Ethernet Switch/Routing
Use Scenario: Providing synchronized 100 MHz HCSL clocks to multiple PCIe Gen 3/4 switch ASICs and endpoint devices in a server backplane. IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent, low-jitter PCIe reference clocks with SRNS compliance and spread-spectrum capability. Use Value: Eliminates four discrete oscillators; ensures sub-0.32 ps RMS jitter per lane to meet PCIe Gen 4 eye diagram mask requirements.	Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10/25 GbE PHYs, packet processors, and switch fabric interfaces. IC Role / Device Role / Timing Role: Any-frequency clock synthesizer providing exact Ethernet line rates with deterministic phase relationships across ports. Use Value: Enables single-chip timing for multi-rate switches; supports IEEE 802.3bj/ck jitter budgets via hardware-programmable phase offsets.
Broadcast Video Timing	FPGA & Processor Clocking
Use Scenario: Delivering SMPTE ST 2082 (12G-SDI), ST 2081 (6G-SDI), and ST 424 (3G-SDI) reference clocks (27/74.25/148.5 MHz) to video encoder/decoder ICs. IC Role / Device Role / Timing Role: Precision quad clock generator with ultra-low jitter and programmable output formats matching SDI receiver input requirements. Use Value: Maintains <10 ps pk-pk period jitter across all outputs - critical for maintaining SDI eye opening and minimizing bit error rate.	Use Scenario: Supplying core, memory, and I/O clocks to Xilinx Versal or Intel Agilex FPGAs, including DDR4/5 controller clocks and transceiver reference clocks. IC Role / Device Role / Timing Role: Configurable clock source supporting mixed-voltage domains (1.0 V core, 1.2 V memory, 1.8 V I/O) with independent phase alignment. Use Value: Reduces BOM count by replacing multiple fixed-frequency oscillators and buffers; enables dynamic reconfiguration during FPGA partial reconfiguration.

PCIe Gen 1–4 Switch Timing

Ethernet Switch/Routing

Use Scenario: Providing synchronized 100 MHz HCSL clocks to multiple PCIe Gen 3/4 switch ASICs and endpoint devices in a server backplane.

IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent, low-jitter PCIe reference clocks with SRNS compliance and spread-spectrum capability.

Use Value: Eliminates four discrete oscillators; ensures sub-0.32 ps RMS jitter per lane to meet PCIe Gen 4 eye diagram mask requirements.

Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10/25 GbE PHYs, packet processors, and switch fabric interfaces.

IC Role / Device Role / Timing Role: Any-frequency clock synthesizer providing exact Ethernet line rates with deterministic phase relationships across ports.

Use Value: Enables single-chip timing for multi-rate switches; supports IEEE 802.3bj/ck jitter budgets via hardware-programmable phase offsets.

Broadcast Video Timing

FPGA & Processor Clocking

Use Scenario: Delivering SMPTE ST 2082 (12G-SDI), ST 2081 (6G-SDI), and ST 424 (3G-SDI) reference clocks (27/74.25/148.5 MHz) to video encoder/decoder ICs.

IC Role / Device Role / Timing Role: Precision quad clock generator with ultra-low jitter and programmable output formats matching SDI receiver input requirements.

Use Value: Maintains <10 ps pk-pk period jitter across all outputs - critical for maintaining SDI eye opening and minimizing bit error rate.

Use Scenario: Supplying core, memory, and I/O clocks to Xilinx Versal or Intel Agilex FPGAs, including DDR4/5 controller clocks and transceiver reference clocks.

IC Role / Device Role / Timing Role: Configurable clock source supporting mixed-voltage domains (1.0 V core, 1.2 V memory, 1.8 V I/O) with independent phase alignment.

Use Value: Reduces BOM count by replacing multiple fixed-frequency oscillators and buffers; enables dynamic reconfiguration during FPGA partial reconfiguration.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output programmable clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D06174-GM	Higher integration: 8 outputs, integrated crystal, lower jitter (0.35 ps RMS), but larger 5 × 5 mm 32-QFN package.	Preferred for new designs requiring >4 outputs or crystal-integrated simplicity; not drop-in compatible due to pin count and footprint change.	Select when needing more outputs or tighter jitter; requires PCB redesign and firmware update for ClockBuilder Pro v2.x.
ICS8430I-01T	Fixed-frequency quad LVDS generator (no I²C programming); 1.2 ps RMS jitter; 3.3 V only; no spread spectrum or phase control.	Suitable only for static clock trees where frequencies never change; lacks PCIe SRNS compliance and hardware tuning features.	Choose only for cost-sensitive, unchanging clock architectures where programmability is unnecessary and jitter margin is sufficient.

Compared with Si5332A-D06174-GM and ICS8430I-01T, SI5338N-B06174-GMR uniquely balances field-programmability, PCIe Gen 4 readiness, and compact 24-QFN footprint - making it optimal for space-constrained, multi-standard timing upgrades without full platform redesign.

Availability

SI5338N-B06174-GMR is available at Aetrix Electronics and suitable for PCIe switch timing, 10GbE routing, broadcast video synchronization, and FPGA clocking applications requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.

Supply support for SI5338N-B06174-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and industrial markets.

The SI5338 family was engineered to replace multiple fixed-frequency oscillators in high-speed serial interface systems, delivering programmable, low-jitter clock synthesis in minimal footprint for PCIe, Ethernet, and broadcast video platforms.

FAQ

What is the primary function of the SI5338N-B06174-GMR in a PCIe Gen 4 system?

The SI5338N-B06174-GMR serves as a quad-output, low-jitter clock generator delivering compliant 100 MHz HCSL reference clocks to PCIe Gen 4 switches and endpoints. Its 0.15–0.45 ps RMS jitter meets PCIe Base Spec 4.0 common clock requirements, and its SRNS mode supports separate reference architectures. The SI5338N-B06174-GMR enables single-chip timing consolidation while maintaining signal integrity across high-speed lanes.

Does the SI5338N-B06174-GMR support spread-spectrum clocking (SSC), and how is it configured?

Yes, the SI5338N-B06174-GMR supports hardware- and I²C-configurable spread-spectrum clocking on any output, with adjustable spread (0.5–5.0%), modulation rate (33–63 kHz), and direction (down-spread default). Configuration is performed via ClockBuilder Pro software or direct register writes to the SSC control registers; no external components are required. This feature reduces EMI without impacting SI5338N-B06174-GMR's jitter performance or system timing margins.

Can the SI5338N-B06174-GMR generate different output voltages simultaneously on its four channels?

Yes, the SI5338N-B06174-GMR supports independent output buffer supplies (VDDO0–VDDO3), allowing simultaneous 1.8 V LVDS, 2.5 V HCSL, 3.3 V CMOS, and 1.5 V SSTL outputs. Each VDDO pin powers its associated CLKxA/CLKxB pair, enabling direct interfacing with mixed-voltage SoCs, FPGAs, and PHYs without external level shifters - a key capability confirmed in Table 6 and Section 3.4 of the SI5338N-B06174-GMR datasheet.

How does the SI5338N-B06174-GMR handle loss-of-signal (LOS) detection, and what is the response time?

The SI5338N-B06174-GMR provides dedicated loss-of-signal detection on all six input pins (IN1–IN6), with typical detection time of 2.6–5 µs and release time of 0.01–1 µs. Detected events trigger the open-drain INTR pin and corresponding status bits in the interrupt register. This fast, hardware-based monitoring allows real-time failover to backup references - a critical function validated in Table 5 and Section 3.6 of the SI5338N-B06174-GMR datasheet.

Is ClockBuilder Pro software required to configure the SI5338N-B06174-GMR, or can it be programmed in-system?

ClockBuilder Pro is recommended for initial configuration and validation but is not mandatory for in-system operation. The SI5338N-B06174-GMR supports full I²C/SMBus programming (100/400 kHz) for runtime frequency, phase, format, and SSC updates. Pre-programmed OTP versions (like SI5338N-B06174-GMR) ship with factory-loaded configurations, enabling immediate use without host intervention - though dynamic reprogramming remains fully supported via the SI5338N-B06174-GMR's I²C interface.

SI5338N-B06174-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338N-B06174-GMR FAQ

1.How can I place an order for SI5338N-B06174-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338N-B06174-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338N-B06174-GMR reliable?

The price and inventory of SI5338N-B06174-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338N-B06174-GMR is usually 5 days.

3.What payment methods are accepted for SI5338N-B06174-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338N-B06174-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338N-B06174-GMR?

SI5338N-B06174-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338N-B06174-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338N-B06174-GMR?

For technical support, including SI5338N-B06174-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338N-B06174-GMR requirements.

6.How does Aetrix verify that SI5338N-B06174-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338N-B06174-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338N-B06174-GMR meets industry standards.

7.What is the process for return or replacement of SI5338N-B06174-GMR?

All SI5338N-B06174-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338N-B06174-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338N-B06174-GMR part is unused and in its original packaging.

Return procedure for SI5338N-B06174-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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