Skyworks Solutions Inc. SI5338N-B06176-GM

Overview

SI5338N-B06176-GM from Skyworks Solutions is a quad-output, I²C-programmable clock generator implementing MultiSynth™ PLL architecture to synthesize independent frequencies up to 710 MHz per output with 0 ppm precision, 0.7 ps RMS phase jitter (typ), and PCIe Gen 1–4 Common Clock & Gen 3 SRNS compliance. It serves as a low-jitter timing source for FPGA/processor clocking, Ethernet switching, and broadcast video systems.

For engineers reviewing the SI5338N-B06176-GM datasheet, SI5338N-B06176-GM pinout, SI5338N-B06176-GM application, or SI5338N-B06176-GM equivalent, key selection criteria include differential output format support (LVPECL/LVDS/HCSL), independent per-output voltage control (1.5–3.3 V), spread-spectrum capability (0.5–5.0% down-spread), and 24-QFN package compatibility with PCIe jitter requirements.

Technical Context

The SI5338N-B06176-GM integrates a two-stage synthesis architecture: a high-stability PLL stage (loop bandwidth 1.6 MHz) locks to an input reference (5–710 MHz), followed by four independent MultiSynth™ fractional-N dividers enabling any-frequency generation on each of four differential outputs. Each output driver supports configurable signal formats and supply voltages without shared constraints.

It features dedicated loss-of-lock and loss-of-signal alarms, programmable initial phase offset (±45 ns), and glitchless frequency increment/decrement in 1 ppm steps via pin control or I²C. The device operates across –40 to +85 °C with core supply options at 1.8 V, 2.5 V, or 3.3 V and output buffer supplies independently set from 1.4 V to 3.63 V.

Key Specifications

Pinout & Package

The SI5338N-B06176-GM uses a 24-lead QFN package (4 mm × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin assignments are fixed per Skyworks' Si5338 family specification and validated for this variant.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output programmable clock generator applications.

Compared with Si5338A-B06176-GM, the SI5338N-B06176-GM offers identical hardware functionality but different factory OTP settings-requiring no reprogramming if its default configuration aligns with the design. Against LMK04832, it trades deterministic latency and dual-loop cleaning for lower power, smaller footprint, and simpler configuration.

Availability

SI5338N-B06176-GM is available at Aetrix Electronics and suitable for PCIe Gen 4 switch designs, 10 GbE routing platforms, and broadcast video timing systems requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for SI5338N-B06176-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and power management ICs for infrastructure, automotive, and industrial markets.

The Si5338 product line delivers highly configurable, low-jitter clock generation for high-speed digital systems-including PCIe, Ethernet, and broadcast video-where precise frequency synthesis and minimal phase noise are critical.

FAQ

What is the default factory configuration of the SI5338N-B06176-GM?

The SI5338N-B06176-GM ships with one-time-programmable (OTP) memory preloaded with a specific frequency configuration optimized for common PCIe or Ethernet use cases. Unlike the Si5338A variant, the 'N' suffix indicates a non-reprogrammable OTP image; full customization requires ClockBuilder Pro and I²C programming. The SI5338N-B06176-GM retains all functional capabilities of the Si5338 family but starts from a defined baseline state.

Does the SI5338N-B06176-GM support PCIe Gen 4 Common Clock compliance?

Yes, the SI5338N-B06176-GM meets PCIe Gen 4 Common Clock jitter requirements with ≤0.45 ps RMS (1.5 MHz–50 MHz band) when configured per Skyworks' recommended PLL bandwidth (2–4 MHz) and CDR settings. This is verified using the Skyworks PCIe Clock Jitter Tool and aligns with PCI-SIG Base Specification 4.0 rev. 0.5. The SI5338N-B06176-GM achieves this without external jitter cleaners due to its integrated MultiSynth™ architecture and low-noise VCO.

Can the SI5338N-B06176-GM generate both LVDS and HCSL outputs simultaneously?

Yes, the SI5338N-B06176-GM supports mixed output formats: CLK0A/B can be configured as LVDS (1.2 V common-mode), CLK1A/B as HCSL (0.375 V common-mode), and CLK2A/B as CMOS-all concurrently. Each output pair uses its own VDDO supply (e.g., 2.5 V for LVDS, 1.8 V for HCSL), enabling direct interface to diverse receivers without level shifters. This capability is confirmed in the Si5338 datasheet Section 3.4 and Table 6.

What is the minimum input reference frequency supported by the SI5338N-B06176-GM in PLL mode?

In active PLL mode, the SI5338N-B06176-GM requires a minimum input reference frequency of 5 MHz across all input types (differential, CMOS, SSTL, HSTL). Crystal inputs are limited to 8–30 MHz per Tables 8–11. Operation below 5 MHz is only supported in clock buffer (PLL bypass) mode, where loss-of-signal detection is disabled. This 5 MHz lower bound ensures stable phase detector operation and loop filter performance per Skyworks' design validation.

How does the SI5338N-B06176-GM handle loss-of-lock and loss-of-signal conditions?

The SI5338N-B06176-GM asserts the open-drain INTR pin low upon detecting loss-of-lock (tLOL = 5–10 ms) or loss-of-signal (tLOS = 2.6–5 µs). These status flags are latched until cleared via I²C register write or hardware reset. The device continues outputting the last valid clock during alarm states unless disabled via OEB pin. This behavior is documented in Sections 3.6 and 7 of the Si5338 datasheet and applies identically to the SI5338N-B06176-GM variant.