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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338N-B06177-GMR

Name: SI5338N-B06177-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338N-B06177-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338N-B06177-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338N-B06177-GMR.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

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Product details

Overview

SI5338N-B06177-GMR from Skyworks Solutions is a quad-output, I²C-programmable clock generator implementing MultiSynth™ frequency synthesis. It delivers four independent, any-frequency clocks (0.16–710 MHz) with 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and configurable LVPECL/LVDS/HCSL/CMOS/SSTL outputs - deployed in high-speed Ethernet switches and FPGA timing systems.

For engineers reviewing the SI5338N-B06177-GMR datasheet, SI5338N-B06177-GMR pinout, SI5338N-B06177-GMR application, or SI5338N-B06177-GMR equivalent, key selection criteria include differential output jitter performance at 125 MHz (0.7 ps RMS), independent per-output voltage control (1.5–3.3 V), and support for external crystal (8–30 MHz), CMOS (5–200 MHz), or differential inputs (5–710 MHz).

Technical Context

The SI5338N-B06177-GMR integrates a two-stage PLL architecture: a high-stability reference stage (with programmable R-divider) feeding a fractional-N MultiSynth™ VCO stage (Fvco = 3.2–4.0 GHz), enabling integer or fractional synthesis per output. Each of the four output drivers operates independently with dedicated M/N/P dividers and configurable output format registers.

It supports both free-running synthesis and zero-delay buffer mode via external feedback, with loss-of-lock and loss-of-signal monitoring, independent 1 ppm frequency increment/decrement, and <20 ps step phase adjustment on all outputs - all controlled via I²C/SMBus interface with OTP NVM storage.

Key Specifications

Parameter	Value and Actual Design Meaning
Output count & type	4 differential clock outputs (CLK0A/B through CLK3A/B), supporting LVPECL/LVDS/HCSL/CML/SSTL/HSTL/CMOS formats
Frequency range	0.16–710 MHz per output; >350 MHz limited to two unique frequencies simultaneously (Fvco/4 and Fvco/6)
Phase jitter (RMS)	0.7 ps typical (12 kHz–20 MHz), measured at 125 MHz LVDS output with 25 MHz crystal reference
Input flexibility	Supports 8–30 MHz crystal, 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL, or 5–710 MHz differential reference
Supply & power	1.8/2.5/3.3 V core supply; 1.5/1.8/2.5/3.3 V per-output buffer supply; 45 mA typical core current at 100 MHz on all outputs
Operating temperature	–40 °C to +85 °C ambient, qualified for industrial and telecom line card deployment
Compliance	PCIe Gen 1/2/3/4 Common Clock; PCIe Gen 3 SRNS; JEDEC JESD65-compliant cycle-cycle jitter

Pinout & Package

SI5338N-B06177-GMR is housed in a 4 mm × 4 mm, 24-pin QFN package with exposed thermal pad (RoHS-compliant, lead-free). Pin 1 is top-left corner (IN1), pin 24 is bottom-right (GND); pinout follows standard Si5338 layout with dual differential inputs (IN1/IN2, IN5/IN6), single-ended inputs (IN3/IN4), four differential output pairs (CLK0A/B–CLK3A/B), three VDDO supplies, shared VDD core, SCL/SDA/I²C interface, INTR alarm, and reserved ground.

Pin/Terminal	Circuit Role	Design Meaning
IN1 / IN2	Differential input pair 1	Accepts 5–710 MHz AC-coupled differential clock; requires external 100 Ω termination
CLK0A / CLK0B	Differential output pair 0	Configurable LVPECL/LVDS/HCSL/CML; independently set frequency, format, and VDDO0 voltage
VDDO0 / VDDO1 / VDDO2 / VDDO3	Output buffer supply rails	Each powers one output pair; supports 1.5/1.8/2.5/3.3 V for level translation and signal integrity optimization
SCL / SDA	I²C serial interface	Standard SMBus-compatible 2-wire bus for configuration, status readback, and runtime reprogramming
INTR	Interrupt output	Open-drain active-low signal indicating loss-of-lock, loss-of-signal, or other fault conditions

Key Features

Feature	Design Value
MultiSynth™ synthesis	Enables true zero-ppm frequency accuracy across all four outputs without external VCXO or loop filter components
Independent output control	Each output supports separate frequency, format, voltage, phase offset (±45 ns), and spread-spectrum modulation (0.5–5.0%, 33–63 kHz)
PCIe Gen 4 timing compliance	Meets 0.15–0.45 ps RMS jitter requirement under Common Clock architecture with 2–5 MHz PLL bandwidth
Glitchless frequency tuning	Hardware-supported 1 ppm step frequency increment/decrement via PINC/FDEC pins, updating in ≤667 ns
Low-power operation	45 mA typical core current at full load; 12 mA in buffer-only mode; optimized PSRR across 1.8/2.5/3.3 V supply range

Applications

Ethernet Switch Timing	PCIe Gen 4 Server Clocking
Use Scenario: 10 GbE/25 GbE switch fabric requiring synchronous, low-jitter clocks for SerDes lanes and packet processing ASICs. IC Role / Device Role / Timing Role: Primary clock generator providing four independent 156.25 MHz LVDS clocks with matched skew and sub-1 ps RMS jitter. Use Value: Enables deterministic latency and BER <1e−12 by meeting IEEE 802.3bj jitter masks without external jitter cleaners.	Use Scenario: Dual-CPU server motherboard needing PCIe Gen 4 reference clocks for CPU, GPU, and NVMe controllers. IC Role / Device Role / Timing Role: Common Clock source delivering 100 MHz HCSL clocks compliant with PCIe Base Spec 4.0 rev 0.5 SRNS requirements. Use Value: Eliminates need for four discrete oscillators while maintaining 0.32 ps RMS jitter at 100 MHz under CDR = 10 MHz test condition.
FPGA-Based Video Processing	Telecom Line Card Synchronization
Use Scenario: Broadcast video encoder using Xilinx Ultrascale+ FPGA with multiple clock domains (27 MHz SDI, 74.25 MHz HDMI, 148.5 MHz DP). IC Role / Device Role / Timing Role: Any-frequency synthesizer generating exact pixel-clock frequencies from a single 25 MHz crystal reference. Use Value: Reduces BOM count and board area versus discrete oscillators; enables field-upgradable clock rates via I²C reprogramming.	Use Scenario: OTN/SONET line card requiring synchronization to Stratum 3E reference with holdover capability. IC Role / Device Role / Timing Role: Frequency translator converting 19.44 MHz OC-12 reference to 155.52 MHz, 622.08 MHz, and 2.488 Gbps line rates. Use Value: Achieves 0.7 ps RMS OC-12 random jitter (12 kHz–5 MHz) while supporting loss-of-signal detection for automatic failover.

Ethernet Switch Timing

PCIe Gen 4 Server Clocking

Use Scenario: 10 GbE/25 GbE switch fabric requiring synchronous, low-jitter clocks for SerDes lanes and packet processing ASICs.

IC Role / Device Role / Timing Role: Primary clock generator providing four independent 156.25 MHz LVDS clocks with matched skew and sub-1 ps RMS jitter.

Use Value: Enables deterministic latency and BER <1e−12 by meeting IEEE 802.3bj jitter masks without external jitter cleaners.

Use Scenario: Dual-CPU server motherboard needing PCIe Gen 4 reference clocks for CPU, GPU, and NVMe controllers.

IC Role / Device Role / Timing Role: Common Clock source delivering 100 MHz HCSL clocks compliant with PCIe Base Spec 4.0 rev 0.5 SRNS requirements.

Use Value: Eliminates need for four discrete oscillators while maintaining 0.32 ps RMS jitter at 100 MHz under CDR = 10 MHz test condition.

FPGA-Based Video Processing

Telecom Line Card Synchronization

Use Scenario: Broadcast video encoder using Xilinx Ultrascale+ FPGA with multiple clock domains (27 MHz SDI, 74.25 MHz HDMI, 148.5 MHz DP).

IC Role / Device Role / Timing Role: Any-frequency synthesizer generating exact pixel-clock frequencies from a single 25 MHz crystal reference.

Use Value: Reduces BOM count and board area versus discrete oscillators; enables field-upgradable clock rates via I²C reprogramming.

Use Scenario: OTN/SONET line card requiring synchronization to Stratum 3E reference with holdover capability.

IC Role / Device Role / Timing Role: Frequency translator converting 19.44 MHz OC-12 reference to 155.52 MHz, 622.08 MHz, and 2.488 Gbps line rates.

Use Value: Achieves 0.7 ps RMS OC-12 random jitter (12 kHz–5 MHz) while supporting loss-of-signal detection for automatic failover.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D06177-GM	Higher integration: 8 outputs, integrated LDOs, lower jitter (0.35 ps RMS), supports JESD204B deterministic latency	Targets JESD204B ADC/DAC sync and multi-core SoC clock trees where output count and deterministic delay matter	Select when >4 outputs, sub-0.5 ps jitter, or deterministic latency control are required; not pin-compatible
ICS853S02AGT	Fixed-frequency, non-programmable; 2 LVDS outputs; 1.2 ps RMS jitter; no I²C interface or spread spectrum	Suitable for cost-sensitive, static-clock applications like legacy PCIe Gen 2 add-in cards	Select only for fixed-frequency use cases where programmability and jitter margin are secondary to unit cost

Compared with Si5332A-D06177-GM, SI5338N-B06177-GMR offers lower system cost and simpler configuration for 4-output needs, while ICS853S02AGT lacks frequency agility and jitter headroom required for PCIe Gen 4 or multi-standard video timing.

Availability

SI5338N-B06177-GMR is available at Aetrix Electronics and suitable for Ethernet switch/router design, PCIe Gen 4 server platforms, and broadcast video timing applications requiring stable component supply and long-term manufacturability.

Supply support for SI5338N-B06177-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5338 product line was designed to replace multiple discrete oscillators with a single, software-configurable clock generator for high-speed digital systems - emphasizing low jitter, flexible I/O, and robust industrial temperature operation.

FAQ

What is the maximum output frequency supported by SI5338N-B06177-GMR?

The SI5338N-B06177-GMR supports up to 710 MHz on LVPECL/LVDS/CML outputs, 350 MHz on SSTL/HSTL, and 250 MHz on HCSL. However, only two unique frequencies above 350 MHz can be generated simultaneously (Fvco/4 and Fvco/6), as specified in the functional description and Table 6 of the datasheet. All outputs remain fully programmable within their respective ranges.

Does SI5338N-B06177-GMR support PCIe Gen 4 Common Clock compliance?

Yes, SI5338N-B06177-GMR meets PCIe Gen 4 Common Clock jitter requirements: 0.15–0.45 ps RMS (12 kHz–20 MHz) at 100 MHz HCSL output with PLL bandwidth set to 2–5 MHz and CDR = 10 MHz, as validated per PCI-Express Base Specification 4.0 rev 0.5 and documented in Table 12 of the datasheet.

Can SI5338N-B06177-GMR operate with a 12 MHz crystal?

Yes, SI5338N-B06177-GMR supports crystals from 8–30 MHz, including 12 MHz. The device's on-chip crystal oscillator supports load capacitances of 11–13 pF (supported) and recommends 17–19 pF (optimal); register adjustments per AN360 allow reliable startup and stability with standard 12 pF crystals.

How many independent supply voltages does SI5338N-B06177-GMR support for its outputs?

SI5338N-B06177-GMR provides four independent output buffer supply rails - VDDO0, VDDO1, VDDO2, and VDDO3 - each configurable for 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This enables simultaneous LVDS (1.8 V), HCSL (1.8 V), and CMOS (3.3 V) outputs without level-shifting components.

Is SI5338N-B06177-GMR pin-compatible with other Si5338 variants?

Yes, all Si5338 variants - including SI5338N-B06177-GMR - share the same 24-pin QFN package and pinout. Differences lie in factory-programmed configuration (e.g., default frequencies, output formats, spread-spectrum settings), but hardware layout, PCB footprint, and signal routing are identical across the family.

SI5338N-B06177-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338N-B06177-GMR FAQ

1.How can I place an order for SI5338N-B06177-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338N-B06177-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338N-B06177-GMR reliable?

The price and inventory of SI5338N-B06177-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338N-B06177-GMR is usually 5 days.

3.What payment methods are accepted for SI5338N-B06177-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338N-B06177-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338N-B06177-GMR?

SI5338N-B06177-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338N-B06177-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338N-B06177-GMR?

For technical support, including SI5338N-B06177-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338N-B06177-GMR requirements.

6.How does Aetrix verify that SI5338N-B06177-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338N-B06177-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338N-B06177-GMR meets industry standards.

7.What is the process for return or replacement of SI5338N-B06177-GMR?

All SI5338N-B06177-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338N-B06177-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338N-B06177-GMR part is unused and in its original packaging.

Return procedure for SI5338N-B06177-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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