Skyworks Solutions Inc. SI5338N-B06178-GM

Overview

SI5338N-B06178-GM from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation across –40 to +85 °C. It replaces up to four crystal oscillators in high-speed serial interface timing applications such as PCIe root complexes and Ethernet switch fabric clocking.

For engineers reviewing the SI5338N-B06178-GM datasheet, SI5338N-B06178-GM pinout, SI5338N-B06178-GM application, or SI5338N-B06178-GM equivalent, key selection criteria include its MultiSynth™-based any-frequency synthesis (0.16–710 MHz per output), independent output voltage support (1.5/1.8/2.5/3.3 V), spread-spectrum capability (0.5–5.0% down-spread), and 24-QFN package compatibility with space-constrained FPGA/ASIC timing designs.

Technical Context

The SI5338N-B06178-GM implements a two-stage PLL architecture: a high-stability reference stage followed by four independent MultiSynth™ fractional-N synthesizers, each driving a configurable output buffer. Its input flexibility supports external crystals (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), and differential clocks (5–710 MHz).

Each output driver supports LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats with independent voltage supply (VDDOx), programmable phase offset (±45 ns), and glitchless frequency increment/decrement (1 ppm steps). The device operates from a single 1.8/2.5/3.3 V core supply and delivers <20 ps phase step resolution with loss-of-lock and loss-of-signal monitoring.

Key Specifications

Pinout & Package

SI5338N-B06178-GM uses a 24-lead, 4 × 4 mm QFN package with exposed thermal pad. Pin 1 is top-left corner (IN1), pin 24 is bottom-right (GND). Pin functions are validated per Skyworks Si5338 Rev. 1.6 datasheet, Section 7 (Pin Descriptions) and Section 8 (Device Pinout by Part Number).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output clock generator applications.

Compared with Si5338A-B06178-GM, SI5338N-B06178-GM offers identical hardware but unprogrammed OTP - enabling full custom configuration via ClockBuilder Pro. Against LMK04832RHAR, it trades JESD204B features for lower power, smaller footprint, and superior independent output flexibility in multi-protocol serial timing.

Availability

SI5338N-B06178-GM is available at Aetrix Electronics and suitable for PCIe Gen 4 root complexes, 10 GbE switch fabrics, and FPGA-based broadcast video equipment requiring stable component supply and long-term lifecycle assurance.

Supply support for SI5338N-B06178-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and power management ICs.

The Si5338 product line was designed for high-performance, multi-protocol serial interface timing - specifically targeting PCIe, Ethernet, Fibre Channel, and broadcast video systems requiring ultra-low jitter, flexible frequency synthesis, and compact packaging.

FAQ

What is the default configuration of SI5338N-B06178-GM at power-up?

The SI5338N-B06178-GM ships with unprogrammed OTP memory, meaning it powers up in reset state with no valid clock output until configured via I²C. Unlike factory-programmed variants (e.g., SI5338A-B06178-GM), SI5338N-B06178-GM requires ClockBuilder Pro or custom firmware initialization before generating clocks. This ensures full design flexibility but mandates inclusion of I²C programming in system boot sequence. SI5338N-B06178-GM does not output clocks until registers are written and PLLs locked.

Does SI5338N-B06178-GM support PCIe Gen 4 Separate Reference No Spread (SRNS) mode?

Yes, SI5338N-B06178-GM supports PCIe Gen 4 SRNS mode with 0.15–0.45 ps RMS jitter (typ/max) when configured per Skyworks AN562 guidelines: PLL bandwidth set to 2–4 MHz, CDR frequency at 10 MHz, and no spread-spectrum enabled. This compliance is verified using the Skyworks PCIe Clock Jitter Tool and Agilent 90804 oscilloscope per PCI-SIG Base Spec 4.0 rev. 0.5. SI5338N-B06178-GM achieves this using its dual-loop architecture and low-noise VCO design.

Can SI5338N-B06178-GM generate three different frequencies above 350 MHz simultaneously?

No, SI5338N-B06178-GM cannot generate three unique frequencies above 350 MHz simultaneously. Per Skyworks Si5338 Rev. 1.6 datasheet Table 6 Note 6, only two distinct frequencies above 350 MHz are supported concurrently - specifically Fvco/4 and Fvco/6 - due to VCO frequency division constraints. Attempting to configure a third >350 MHz output results in invalid MultiSynth settings or failure to lock. SI5338N-B06178-GM supports up to four outputs, but high-frequency allocation must observe this limitation.

What is the maximum output current per VDDO pin on SI5338N-B06178-GM?

SI5338N-B06178-GM does not specify a maximum current per VDDO pin in absolute terms; instead, total output buffer supply current (IDDOx) depends on output format and frequency. For example, LVPECL at 710 MHz draws ≤30 mA per VDDO rail, LVDS at 710 MHz draws ≤8 mA, and CMOS at 200 MHz draws ≤18 mA (3.3 V VDDO). These values are measured with specified loads and represent worst-case per-rail consumption. SI5338N-B06178-GM requires proper decoupling (0.1 µF + 10 µF per VDDO) to maintain PSRR and jitter performance.

How does the INTR pin function on SI5338N-B06178-GM?

The INTR pin on SI5338N-B06178-GM is an open-drain interrupt output that asserts low upon detection of loss-of-lock (LOL), loss-of-signal (LOS), or PLL unlock events. It remains asserted until cleared via I²C register write (Register 0x000C, bit 0) or hardware reset. The pin supports 3 mA sink current with VOL ≤ 0.4 V and rise/fall time <10 ns (1 kΩ pull-up). INTR enables real-time clock health monitoring in mission-critical systems without polling. SI5338N-B06178-GM uses this pin to signal timing faults before system-level failures occur.