Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338N-B06178-GMR

Name: SI5338N-B06178-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338N-B06178-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: SI5338N-B06178-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338N-B06178-GMR.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:4,831

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

SI5338N-B06178-GMR from Skyworks Solutions is a quad-output, I²C-programmable clock generator implementing MultiSynth™ frequency synthesis. It delivers four independent, any-frequency clocks (0.16–710 MHz) with 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and configurable LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL outputs - used in high-speed serial interface timing for FPGA-based telecom line cards.

For engineers reviewing the SI5338N-B06178-GMR datasheet, SI5338N-B06178-GMR pinout, SI5338N-B06178-GMR application, or SI5338N-B06178-GMR equivalent, key selection criteria include differential output jitter performance at 125 MHz (0.7 ps RMS), PCIe Gen 4 common-clock RMS jitter (0.15–0.45 ps), independent per-output voltage control (1.5/1.8/2.5/3.3 V), and 24-QFN package compatibility with space-constrained board layouts.

Technical Context

The SI5338N-B06178-GMR integrates a dual-stage PLL architecture: a reference-stage PLL locks to one of six input sources (crystal, CMOS, SSTL/HSTL, or differential), followed by four independent MultiSynth™ fractional-N synthesizers. Each synthesizer drives a fully configurable output stage supporting format, voltage, spread-spectrum, phase offset, and frequency increment/decrement control.

It supports external feedback for zero-delay mode, loss-of-lock and loss-of-signal alarms, and I²C/SMBus programming with ClockBuilder Pro configuration software. The device operates across –40 to +85 °C with core supply options of 1.8 V, 2.5 V, or 3.3 V and output buffer supplies from 1.4 V to 3.63 V.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 4 common-clock jitter spec (0.15–0.45 ps RMS).
Output Frequency Range	0.16–710 MHz per channel; supports up to two >350 MHz outputs simultaneously (Fvco/4 & Fvco/6).
Input Reference Support	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz).
Output Formats	LVPECL, LVDS, HCSL, CML, CMOS, SSTL, HSTL - each independently selectable per channel.
Supply Voltages	Core: 1.8/2.5/3.3 V; Output buffers: 1.4–3.63 V, configurable per driver (VDDO0–VDDO3).
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch - compatible with standard reflow profiles and high-density routing.
Operating Temperature	–40 to +85 °C ambient; validated for industrial and telecom infrastructure deployment.

Pinout & Package

SI5338N-B06178-GMR is housed in a 24-lead, 4 × 4 mm QFN package with exposed thermal pad. Pin assignments follow Skyworks' standardized Si5338 pinout: inputs (IN1–IN6), outputs (CLK0A/B through CLK3A/B), power (VDD, VDDO0–VDDO3), control (SCL, SDA, INTR), and reserved ground (RSVD_GND).

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2, IN5, IN6	Differential clock inputs	Accept AC-coupled differential references up to 710 MHz; require external 100 Ω termination.
IN3, IN4	Single-ended clock inputs	Support CMOS/SSTL/HSTL signals (5–350 MHz); VIH/VIL referenced to VDD.
CLK0A/CLK0B – CLK3A/CLK3B	Differential clock outputs	Four independent pairs; each pair supports LVPECL/LVDS/HCSL/CML with programmable swing and common-mode voltage.
VDDO0–VDDO3	Output buffer supplies	Independent 1.4–3.63 V rails per output pair - enables mixed-voltage system interfacing.
SCL, SDA	I²C/SMBus interface	Standard 2-wire serial bus (up to 400 kHz) for register configuration and status readback.
INTR	Interrupt output	Open-drain alarm signal indicating loss-of-lock or loss-of-signal events.

Key Features

Feature	Design Value
MultiSynth™ synthesis	Enables true zero-ppm frequency accuracy on all four outputs - eliminates need for multiple crystals or oscillators.
Independent phase adjustment	±45 ns range in <20 ps steps per output - supports precise skew alignment in multi-lane SerDes systems.
Glitchless frequency tuning	1 ppm step size via PINC/FDEC pins or I²C - allows real-time dynamic frequency scaling without output interruption.
Configurable spread spectrum	0.5–5.0% down-spread at 33–63 kHz modulation rate on any output - reduces EMI in noise-sensitive applications.
PCIe Gen 4 compliance	Validated RMS jitter ≤0.45 ps (10 kHz–50 MHz) in common-clock mode - meets PCI-SIG specification for Gen 4 root complex and endpoint timing.

Applications

PCIe Gen 4 Server Backplane	Ethernet Switch Timing
Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe Gen 4 slots and switch fabric in a 1U server backplane. IC Role / Device Role / Timing Role: Quad-output clock generator delivering low-jitter, phase-aligned clocks to CPU, GPU, NVMe, and switch ICs. Use Value: Enables simultaneous Gen 4 link training with <0.45 ps RMS jitter - avoids link flapping and ensures full 16 GT/s throughput across all lanes.	Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10/25 GbE PHYs and MACs in a modular L2/L3 switch. IC Role / Device Role / Timing Role: Any-frequency clock synthesizer replacing discrete oscillators and providing format-flexible outputs (LVDS/HCSL/CMOS). Use Value: Reduces BOM count by 4× vs. crystal+buffer solutions while maintaining sub-1 ps RMS jitter required for IEEE 802.3by compliance.
FPGA-Based Telecom Line Card	Broadcast Video Frame Sync
Use Scenario: Supplying 155.52 MHz (OC-3), 622.08 MHz (OC-12), and 2.488 GHz (OC-48) clocks to SERDES transceivers and DSPs on a CPRI/eCPRI fronthaul card. IC Role / Device Role / Timing Role: High-stability frequency translator with external feedback support for zero-delay operation relative to network master clock. Use Value: Achieves OC-12 random jitter ≤0.7 ps RMS - meets Telcordia GR-1244-CORE requirements for SONET/SDH transport.	Use Scenario: Distributing genlock-capable 27 MHz, 74.25 MHz, and 148.5 MHz pixel clocks across SMPTE 2110 video processing modules in an IP-based broadcast router. IC Role / Device Role / Timing Role: Low-phase-noise clock generator with programmable initial phase offset for frame-accurate synchronization. Use Value: Supports ±45 ns phase alignment across outputs - eliminates inter-module frame tearing and ensures seamless SDI-to-IP conversion.

PCIe Gen 4 Server Backplane

Ethernet Switch Timing

Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe Gen 4 slots and switch fabric in a 1U server backplane.

IC Role / Device Role / Timing Role: Quad-output clock generator delivering low-jitter, phase-aligned clocks to CPU, GPU, NVMe, and switch ICs.

Use Value: Enables simultaneous Gen 4 link training with <0.45 ps RMS jitter - avoids link flapping and ensures full 16 GT/s throughput across all lanes.

Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10/25 GbE PHYs and MACs in a modular L2/L3 switch.

IC Role / Device Role / Timing Role: Any-frequency clock synthesizer replacing discrete oscillators and providing format-flexible outputs (LVDS/HCSL/CMOS).

Use Value: Reduces BOM count by 4× vs. crystal+buffer solutions while maintaining sub-1 ps RMS jitter required for IEEE 802.3by compliance.

FPGA-Based Telecom Line Card

Broadcast Video Frame Sync

Use Scenario: Supplying 155.52 MHz (OC-3), 622.08 MHz (OC-12), and 2.488 GHz (OC-48) clocks to SERDES transceivers and DSPs on a CPRI/eCPRI fronthaul card.

IC Role / Device Role / Timing Role: High-stability frequency translator with external feedback support for zero-delay operation relative to network master clock.

Use Value: Achieves OC-12 random jitter ≤0.7 ps RMS - meets Telcordia GR-1244-CORE requirements for SONET/SDH transport.

Use Scenario: Distributing genlock-capable 27 MHz, 74.25 MHz, and 148.5 MHz pixel clocks across SMPTE 2110 video processing modules in an IP-based broadcast router.

IC Role / Device Role / Timing Role: Low-phase-noise clock generator with programmable initial phase offset for frame-accurate synchronization.

Use Value: Supports ±45 ns phase alignment across outputs - eliminates inter-module frame tearing and ensures seamless SDI-to-IP conversion.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output programmable clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5338A-B06178-GM	Same silicon die and pinout; differs only in factory-programmed NVM configuration (default output frequencies and formats).	Pre-configured for legacy reference designs; lacks field-programmable flexibility of SI5338N-B06178-GMR.	Select when drop-in replacement for existing Si5338A-based boards is required without reprogramming.
LMK04832RHAT	Two PLLs + eight outputs; higher power (90 mA typ); supports JESD204B deterministic latency; no integrated crystal oscillator circuitry.	Targeted at JESD204B ADC/DAC timing; requires external VCXO; larger 48-QFN package (7 × 7 mm).	Select when deterministic delay control, ultra-low additive jitter (<0.1 ps), or >4 outputs are mandatory - not a pin-compatible substitute.

Compared with Si5338A-B06178-GM, SI5338N-B06178-GMR offers field-programmability via I²C and ClockBuilder Pro, enabling rapid prototyping and design reuse; compared with LMK04832RHAT, it provides smaller footprint and lower power but lacks JESD204B features and deterministic latency control.

Availability

SI5338N-B06178-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 server backplanes, Ethernet switching infrastructure, FPGA-based telecom line cards, and broadcast video timing systems requiring stable component supply and long-term lifecycle support.

Supply support for SI5338N-B06178-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5338 product line was designed specifically for high-performance, multi-protocol clock generation in space-constrained, jitter-sensitive applications such as PCIe, Ethernet, Fibre Channel, and broadcast video - emphasizing programmability, integration, and signal integrity.

FAQ

What is the maximum output frequency supported by SI5338N-B06178-GMR?

The SI5338N-B06178-GMR supports up to 710 MHz on LVPECL/LVDS/CML outputs and 350 MHz on SSTL/HSTL outputs. However, only two unique frequencies above 350 MHz can be generated simultaneously - specifically Fvco/4 and Fvco/6 - due to internal VCO constraints. All outputs maintain 0.7 ps RMS typical phase jitter within their respective rated ranges.

Does SI5338N-B06178-GMR support PCIe Gen 4 timing requirements?

Yes, SI5338N-B06178-GMR is explicitly validated for PCIe Gen 4 common-clock operation, delivering ≤0.45 ps RMS jitter (10 kHz–50 MHz) per PCI-SIG Base Specification 4.0 rev. 0.5. It meets both total jitter and RMS jitter limits for root complex and endpoint timing, and supports Gen 4 SRNS compliance when configured with appropriate PLL bandwidth and CDR settings.

Can SI5338N-B06178-GMR generate different output voltages on each channel?

Yes, SI5338N-B06178-GMR provides independent output buffer supply pins VDDO0 through VDDO3, each configurable from 1.4 V to 3.63 V. This allows simultaneous LVPECL (2.5 V), LVDS (2.5 V), HCSL (1.8 V), and CMOS (3.3 V) outputs - enabling direct interfacing with mixed-voltage ASICs, FPGAs, and PHYs without level-shifting components.

How is SI5338N-B06178-GMR programmed, and is external hardware required?

SI5338N-B06178-GMR is programmed via its I²C/SMBus interface using Skyworks' ClockBuilder Pro software - a free GUI tool that generates register configuration files and supports real-time validation. No external programmer is needed; configuration can be performed in-system using standard microcontroller I²C peripherals or dedicated evaluation boards like the Si5338-EVB.

What crystal frequency ranges does SI5338N-B06178-GMR support?

SI5338N-B06178-GMR supports external crystals from 8 MHz to 30 MHz, segmented into four validated bands: 8–11 MHz, 11–19 MHz, 19–26 MHz, and 26–30 MHz. Each band has specified load capacitance (11–13 pF supported, 17–19 pF recommended), ESR limits (≤300 Ω), and drive-level caps (≤100 µW) - ensuring reliable start-up and long-term stability.

SI5338N-B06178-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338N-B06178-GMR FAQ

1.How can I place an order for SI5338N-B06178-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338N-B06178-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338N-B06178-GMR reliable?

The price and inventory of SI5338N-B06178-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338N-B06178-GMR is usually 5 days.

3.What payment methods are accepted for SI5338N-B06178-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338N-B06178-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338N-B06178-GMR?

SI5338N-B06178-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338N-B06178-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338N-B06178-GMR?

For technical support, including SI5338N-B06178-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338N-B06178-GMR requirements.

6.How does Aetrix verify that SI5338N-B06178-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338N-B06178-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338N-B06178-GMR meets industry standards.

7.What is the process for return or replacement of SI5338N-B06178-GMR?

All SI5338N-B06178-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338N-B06178-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338N-B06178-GMR part is unused and in its original packaging.

Return procedure for SI5338N-B06178-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-09 Counterfeit Electronic Components: How to Detect, Authenticate, and Test Suspect Parts

Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…