Skyworks Solutions Inc. SI5338N-B06180-GM

Overview

SI5338N-B06180-GM from Skyworks Solutions is an I²C-programmable quad clock generator IC with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation across –40 to +85 °C in a 4 × 4 mm 24-QFN package. It replaces up to four crystal oscillators in Ethernet switch/router, processor/FPGA clocking, and broadcast video timing systems.

For engineers reviewing the SI5338N-B06180-GM datasheet, SI5338N-B06180-GM pinout, SI5338N-B06180-GM application, or SI5338N-B06180-GM equivalent, key selection criteria include its MultiSynth™-based any-frequency synthesis (0.16–710 MHz per output), independent output voltage support (1.5/1.8/2.5/3.3 V), spread-spectrum capability (0.5–5.0% spread, 33–63 kHz modulation), and I²C/SMBus programmability with ClockBuilder Pro software integration.

Technical Context

The SI5338N-B06180-GM implements a two-stage PLL architecture: a high-performance integer-N PLL (Stage 1) locks to one of six input references (crystal, CMOS, SSTL/HSTL, or differential), followed by four independent MultiSynth™ fractional-N synthesis blocks (Stage 2) generating each output. Each output driver supports LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats with per-output supply voltage selection and programmable phase offset (±45 ns, <20 ps step).

It features loss-of-lock and loss-of-signal alarms, external feedback mode for zero-delay operation, and independent frequency increment/decrement control (1 ppm steps, glitchless update). The device operates from a single 1.8/2.5/3.3 V core supply with 45 mA typical current draw and integrates OTP NVM for factory or field programming.

Key Specifications

Pinout & Package

SI5338N-B06180-GM is housed in a 24-lead, 4 × 4 mm QFN package with exposed thermal pad. Pin assignments follow Skyworks' standard Si5338 top-view layout (Rev. 1.6).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output clock generator applications.

Compared with Si5332A-D06180-GM and ICS853S02IAGLF, the SI5338N-B06180-GM uniquely delivers four independently programmable outputs with full PCIe Gen 4 and broadcast video timing compliance in a single 4 mm² footprint - making it optimal for complex, multi-standard systems requiring field-upgradable timing.

Availability

SI5338N-B06180-GM is available at Aetrix Electronics and suitable for Ethernet switch/router timing, PCIe Gen 3/4 clocking, and broadcast video/audio timing requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for SI5338N-B06180-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and mobile markets.

The SI5338N-B06180-GM belongs to Skyworks' Si5338 family of programmable clock generators, designed specifically for high-density, multi-protocol timing consolidation in networking, computing, and broadcast equipment.

FAQ

What is the maximum output frequency supported by the SI5338N-B06180-GM?

The SI5338N-B06180-GM supports up to 710 MHz on LVPECL/LVDS/CML outputs, 350 MHz on SSTL/HSTL, 250 MHz on HCSL, and 200 MHz on CMOS outputs. Frequencies above 350 MHz are restricted to two unique values simultaneously (Fvco/4 and Fvco/6) due to VCO architecture constraints - a design consideration confirmed in Table 6 of the official datasheet.

Does the SI5338N-B06180-GM support PCIe Gen 4 Common Clock compliance?

Yes, the SI5338N-B06180-GM is explicitly validated for PCIe Gen 4 Common Clock operation with ≤0.45 ps RMS jitter (10 kHz–50 MHz band), meeting PCI-SIG Base Specification 4.0 rev. 0.5 requirements. This compliance is documented in Table 12 under "PCIe Gen 4, Common Clock" test condition with PLL BW of 2–4 MHz and CDR = 10 MHz.

Can the SI5338N-B06180-GM operate with a single-ended input clock?

Yes, the SI5338N-B06180-GM accepts single-ended CMOS input clocks on pins IN3 and IN4 across 5–200 MHz. Input voltage thresholds are VIH ≥ 0.7×VDD and VIL ≤ 0.3×VDD, with slew rate >1 V/ns recommended for optimal jitter performance - as specified in Table 6 and Section 3.2 of the datasheet.

How is the SI5338N-B06180-GM programmed, and is external hardware required?

The SI5338N-B06180-GM is programmed via its I²C/SMBus interface (SCL/SDA pins) using Skyworks' ClockBuilder Pro software. No external programmer is needed - configuration can be performed in-system using standard I²C host controllers. Factory OTP programming is also supported, and register settings persist through power cycles.

What thermal performance can be expected from the SI5338N-B06180-GM in a typical 4-layer PCB layout?

In still air, the SI5338N-B06180-GM exhibits θJA = 37 °C/W and θJC = 10 °C/W (Table 4). With a properly designed 4-layer board including thermal vias under the exposed pad and ≥1 cm² copper pour, junction temperature rise remains ≤15 °C at 45 mA core current - well within the 150 °C absolute max rating and supporting reliable operation at +85 °C ambient.