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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338N-B06180-GMR

Name: SI5338N-B06180-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338N-B06180-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338N-B06180-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338N-B06180-GMR.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5338N-B06180-GMR from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation across –40 to +85 °C. It replaces up to four crystal oscillators in Ethernet switch/router, processor/FPGA clocking, and broadcast video timing systems.

For engineers reviewing the SI5338N-B06180-GMR datasheet, SI5338N-B06180-GMR pinout, SI5338N-B06180-GMR application, or SI5338N-B06180-GMR equivalent, key selection considerations include its MultiSynth™-based any-frequency synthesis (0.16–710 MHz per output), independent output voltage support (1.5/1.8/2.5/3.3 V), flexible input references (crystal, CMOS, SSTL/HSTL, differential), and I²C/SMBus programmability with ClockBuilder Pro software integration.

Technical Context

The SI5338N-B06180-GMR implements a two-stage PLL architecture: a high-stability integer-N PLL (Stage 1) locks to one of six input sources (IN1–IN6), followed by four independent MultiSynth™ fractional-N synthesizers (Stage 2) generating each output. Each MultiSynth supports integer or fractional mode with <20 ps phase step resolution and 1 ppm frequency increment/decrement capability.

Its output stage provides per-driver configurability for LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats, with independent VDDO supplies enabling mixed-voltage operation. The device supports external feedback for zero-delay mode, loss-of-lock and loss-of-signal alarms, and spread-spectrum clocking (0.5–5.0% spread, 33–63 kHz modulation rate) on any output.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 3 SRNS and Gen 4 common clock jitter requirements
Output Frequency Range	0.16–710 MHz per channel; supports up to two >350 MHz outputs simultaneously (Fvco/4 & Fvco/6)
Input Reference Support	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz)
Output Driver Flexibility	Up to four differential outputs, eight single-ended, or hybrid configuration; each with independent voltage (1.5/1.8/2.5/3.3 V)
Core Supply Voltage	1.8 V (±5%), 2.5 V (±10%), or 3.3 V (±10%) - single supply with excellent PSRR
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch - space-constrained PCBs with thermal resistance θJA = 37 °C/W
Operating Temperature	–40 to +85 °C ambient - qualified for industrial and telecom line card environments

Pinout & Package

SI5338N-B06180-GMR is housed in a 24-lead QFN package (4 × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin assignments follow Skyworks' standard Si5338 top-view layout.

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2, IN5, IN6	Differential input pairs	Accept 5–710 MHz AC-coupled differential clocks; require external 100 Ω termination
IN3, IN4	Single-ended input pins	Support 5–200 MHz CMOS inputs; VIH = 0.7×VDD, VIL = 0.3×VDD
CLK0A/CLK0B to CLK3A/CLK3B	Differential output pairs	Four independent output channels; each configurable as LVPECL/LVDS/HCSL/CML
VDDO0–VDDO3	Output buffer supply pins	Enable per-output voltage setting (1.5/1.8/2.5/3.3 V); decoupling required per channel
VDD	Core supply	Single 1.8/2.5/3.3 V core rail; IDD = 45 mA typical at 100 MHz on all outputs
SCL, SDA	I²C interface	SMBus-compatible serial programming; supports ClockBuilder Pro configuration
INTR	Interrupt output	Open-drain status indicator for loss-of-lock or loss-of-signal events

Key Features

Feature	Design Value
MultiSynth™ synthesis	Enables true zero-ppm frequency accuracy on all four outputs via independent fractional-N dividers
PCIe Gen 4 compliance	Meets 0.15–0.45 ps RMS jitter requirement under common clock architecture with 2–5 MHz PLL bandwidth
Independent phase adjustment	Programmable offset from –45 to +45 ns in <20 ps steps per output - enables precise skew control in multi-clock domains
Spread spectrum clocking	Configurable on any output: 0.5–5.0% down-spread, 33–63 kHz modulation rate - reduces EMI without affecting system timing margins
External feedback mode	Supports zero-delay operation by routing CLKOUT back to feedback input - eliminates propagation delay in synchronous systems

Applications

Ethernet Switch/Router Timing	PCIe Gen 1–4 Clocking
Use Scenario: High-density 1/10 GbE switching fabric requiring synchronized clocks across multiple PHYs, MACs, and packet processors. IC Role / Device Role / Timing Role: Quad clock generator providing four independent, low-jitter reference clocks (e.g., 125 MHz, 156.25 MHz, 250 MHz, 312.5 MHz) with matched phase alignment. Use Value: Eliminates need for four discrete oscillators; achieves <100 ps output-to-output skew and 0.7 ps RMS jitter compliant with IEEE 802.3 and PCIe specifications.	Use Scenario: Server motherboard or add-in card implementing PCIe Gen 3/4 root complex or endpoint with common clock architecture. IC Role / Device Role / Timing Role: Generates 100 MHz common reference for all PCIe lanes plus auxiliary clocks (e.g., 25 MHz for management, 100 MHz for USB 3.x). Use Value: Meets PCIe Gen 4 common clock total jitter limit (≤33.6 ps pk-pk) and SRNS RMS jitter spec (≤0.32 ps) without external jitter cleaners.
Broadcast Video/Audio Timing	Processor & FPGA Clocking
Use Scenario: SMPTE ST 2082/2081 video over IP infrastructure requiring genlock-capable, frame-accurate clock distribution. IC Role / Device Role / Timing Role: Synthesizes SMPTE-compliant frequencies (e.g., 27 MHz, 74.25 MHz, 148.5 MHz) with sub-nanosecond phase stability across four outputs. Use Value: Supports independent phase offset tuning (–45 to +45 ns) and zero-ppm accuracy - enables seamless frame synchronization across encoder, decoder, and transport layers.	Use Scenario: Heterogeneous compute platform integrating ARM SoC, Xilinx Zynq MPSoC, and high-speed ADC/DAC interfaces. IC Role / Device Role / Timing Role: Provides dedicated clocks for CPU subsystem (e.g., 500 MHz), DDR4 memory (e.g., 1200 MHz DDR rate), FPGA logic (e.g., 200 MHz), and SerDes transceivers (e.g., 156.25 MHz). Use Value: Independent MultiSynth™ engines allow simultaneous generation of non-integer-related frequencies with no shared divider constraints - simplifies BOM and layout vs. multiple discrete clock ICs.

Ethernet Switch/Router Timing

PCIe Gen 1–4 Clocking

Use Scenario: High-density 1/10 GbE switching fabric requiring synchronized clocks across multiple PHYs, MACs, and packet processors.

IC Role / Device Role / Timing Role: Quad clock generator providing four independent, low-jitter reference clocks (e.g., 125 MHz, 156.25 MHz, 250 MHz, 312.5 MHz) with matched phase alignment.

Use Value: Eliminates need for four discrete oscillators; achieves <100 ps output-to-output skew and 0.7 ps RMS jitter compliant with IEEE 802.3 and PCIe specifications.

Use Scenario: Server motherboard or add-in card implementing PCIe Gen 3/4 root complex or endpoint with common clock architecture.

IC Role / Device Role / Timing Role: Generates 100 MHz common reference for all PCIe lanes plus auxiliary clocks (e.g., 25 MHz for management, 100 MHz for USB 3.x).

Use Value: Meets PCIe Gen 4 common clock total jitter limit (≤33.6 ps pk-pk) and SRNS RMS jitter spec (≤0.32 ps) without external jitter cleaners.

Broadcast Video/Audio Timing

Processor & FPGA Clocking

Use Scenario: SMPTE ST 2082/2081 video over IP infrastructure requiring genlock-capable, frame-accurate clock distribution.

IC Role / Device Role / Timing Role: Synthesizes SMPTE-compliant frequencies (e.g., 27 MHz, 74.25 MHz, 148.5 MHz) with sub-nanosecond phase stability across four outputs.

Use Value: Supports independent phase offset tuning (–45 to +45 ns) and zero-ppm accuracy - enables seamless frame synchronization across encoder, decoder, and transport layers.

Use Scenario: Heterogeneous compute platform integrating ARM SoC, Xilinx Zynq MPSoC, and high-speed ADC/DAC interfaces.

IC Role / Device Role / Timing Role: Provides dedicated clocks for CPU subsystem (e.g., 500 MHz), DDR4 memory (e.g., 1200 MHz DDR rate), FPGA logic (e.g., 200 MHz), and SerDes transceivers (e.g., 156.25 MHz).

Use Value: Independent MultiSynth™ engines allow simultaneous generation of non-integer-related frequencies with no shared divider constraints - simplifies BOM and layout vs. multiple discrete clock ICs.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5338A-B06180-GM	Same silicon die and pinout; differs only in factory-programmed NVM content (different default frequency configuration)	No functional difference in programmability or performance; identical use cases and register compatibility	Select when pre-configured startup behavior matches legacy design requirements
LMK04832RHAR	Two-stage jitter cleaner + dual-loop PLL; higher power (120 mA), larger 48-QFN package; supports JESD204B deterministic latency	Targeted at RF/data converter timing where ultra-low additive jitter (<50 fs) and deterministic delay matter more than multi-frequency flexibility	Choose for JESD204B-compliant ADC/DAC clock trees; avoid if cost, size, or simple any-frequency synthesis is primary

Compared with Si5338A-B06180-GM, SI5338N-B06180-GMR offers identical hardware functionality but distinct factory-programmed defaults; versus LMK04832RHAR, it trades jitter cleaning capability and deterministic latency for lower cost, smaller footprint, and broader frequency agility across four independent outputs.

Availability

SI5338N-B06180-GMR is available at Aetrix Electronics and suitable for Ethernet switch/router timing, PCIe Gen 1–4 clocking, and broadcast video/audio timing applications requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for SI5338N-B06180-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and mobile markets.

The Si5338 product line delivers highly configurable, low-jitter clock generation for high-speed digital systems - designed specifically to replace multiple fixed-frequency oscillators while supporting PCIe, Ethernet, broadcast, and FPGA timing requirements.

FAQ

What is the default factory configuration of the SI5338N-B06180-GMR?

The SI5338N-B06180-GMR ships with non-volatile memory (NVM) pre-programmed for a specific frequency configuration defined by Skyworks' B06180 variant. Unlike blank or unprogrammed versions, this part powers up with valid clocks on all outputs without requiring I²C initialization - enabling immediate operation in systems lacking boot-time configuration firmware. Its NVM contents are identical to those of the Si5338A-B06180-GM, differing only in marking and ordering code.

Does the SI5338N-B06180-GMR support PCIe Gen 4 separate reference no spread (SRNS) mode?

Yes, the SI5338N-B06180-GMR supports PCIe Gen 4 SRNS mode with 0.11–0.32 ps RMS jitter (typical 0.15 ps) when configured with PLL bandwidth of 2–5 MHz and CDR set to 10 MHz. This compliance is verified per PCI-Express Base Specification 4.0 rev. 0.5 using differential HCSL outputs at 100 MHz. The device's MultiSynth™ architecture ensures zero-ppm accuracy and low deterministic jitter essential for SRNS timing integrity.

Can the SI5338N-B06180-GMR generate three outputs above 350 MHz simultaneously?

No, the SI5338N-B06180-GMR cannot generate three outputs above 350 MHz simultaneously. Its architecture permits only two unique frequencies above 350 MHz at once - specifically Fvco/4 and Fvco/6 - due to VCO frequency constraints and internal divider limitations. Attempting to configure a third >350 MHz output will result in invalid synthesis or failure to lock; valid high-frequency combinations must be validated using ClockBuilder Pro before deployment.

How does the SI5338N-B06180-GMR handle loss-of-signal detection on single-ended inputs?

The SI5338N-B06180-GMR detects loss-of-signal (LOS) on single-ended inputs (IN3/IN4) with 2.6–5 µs response time and releases the alarm within 0.01–1 µs. However, LOS functionality is disabled below 5 MHz in PLL bypass mode; operation down to 1 MHz is supported for clock buffering only. For reliable LOS monitoring, input slew rate must exceed 1 V/ns at the pin, and signal amplitude must remain within –0.1 V to VDD+0.1 V to ensure proper comparator threshold crossing.

Is external crystal load capacitance adjustment required for the SI5338N-B06180-GMR?

Yes, external crystal load capacitance adjustment may be required for the SI5338N-B06180-GMR depending on the selected crystal. The device supports on-chip load capacitance settings of 11–13 pF, but Skyworks recommends 17–19 pF for optimal stability. If using a 12 pF crystal, register adjustments per AN360 must be applied to calibrate the internal capacitors - otherwise, frequency accuracy and startup reliability degrade. Crystal ESR must remain ≤300 Ω (8–11 MHz) or ≤75 Ω (26–30 MHz) for guaranteed operation.

SI5338N-B06180-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338N-B06180-GMR FAQ

1.How can I place an order for SI5338N-B06180-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338N-B06180-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338N-B06180-GMR reliable?

The price and inventory of SI5338N-B06180-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338N-B06180-GMR is usually 5 days.

3.What payment methods are accepted for SI5338N-B06180-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338N-B06180-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338N-B06180-GMR?

SI5338N-B06180-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338N-B06180-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338N-B06180-GMR?

For technical support, including SI5338N-B06180-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338N-B06180-GMR requirements.

6.How does Aetrix verify that SI5338N-B06180-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338N-B06180-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338N-B06180-GMR meets industry standards.

7.What is the process for return or replacement of SI5338N-B06180-GMR?

All SI5338N-B06180-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338N-B06180-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338N-B06180-GMR part is unused and in its original packaging.

Return procedure for SI5338N-B06180-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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