Skyworks Solutions Inc. SI5338N-B09663-GMR
- Part No.:
- SI5338N-B09663-GMR
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Application Specific Clock/Timing
- Package:
- -
- Datasheet:
-
SI5338N-B09663-GMR.pdf
- Description:
- IC CLOCK GENERATOR QUAD 24QFN
- Quantity:
- Payment:

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Product details
Overview
SI5338N-B09663-GMR from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation from 1.8/2.5/3.3 V core supply in a 4 × 4 mm 24-QFN package. It replaces up to four crystal oscillators in high-speed serial interface timing applications.
For engineers reviewing the SI5338N-B09663-GMR datasheet, SI5338N-B09663-GMR pinout, SI5338N-B09663-GMR application, or SI5338N-B09663-GMR equivalent, key selection criteria include PCIe Gen 4 jitter compliance (0.15–0.45 ps RMS), independent output voltage per driver (1.5–3.3 V), MultiSynth™ fractional synthesis resolution (1 ppb), and flexible input support (5–710 MHz differential, 8–30 MHz crystal).
Technical Context
The SI5338N-B09663-GMR implements a two-stage PLL architecture: a high-stability integer-N PLL for reference conditioning followed by four independent MultiSynth™ fractional-N synthesizers - each driving one output pair (CLKxA/CLKxB) with programmable format, voltage, and phase offset. Its synthesis engine supports true zero-ppm accuracy across all outputs via patented MultiSynth™ technology.
It features full I²C/SMBus register access for real-time frequency increment/decrement (1 ppm steps), phase adjustment (<20 ps steps), and spread-spectrum control (0.5–5.0% spread, 33–63 kHz modulation). Input flexibility includes external crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), or differential (5–710 MHz) references.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Phase Jitter (RMS) | 0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 4 common clock spec (≤0.45 ps RMS) |
| Output Count & Type | 4 differential output pairs (CLK0A/B–CLK3A/B); supports LVPECL/LVDS/HCSL/CML/CMOS/SSTL/HSTL |
| Synthesis Resolution | 1 ppb frequency step size; enables exact integer/fractional synthesis without approximation error |
| Input Frequency Range | 8–30 MHz crystal; 5–710 MHz differential; 5–350 MHz SSTL/HSTL; 5–200 MHz CMOS |
| Output Frequency Range | LVPECL/LVDS: 0.16–710 MHz; HCSL: 0.16–250 MHz; CMOS: 0.16–200 MHz; SSTL/HSTL: 0.16–350 MHz |
| Supply Voltages | Core: 1.8/2.5/3.3 V ±10%; Output buffers: independently configurable 1.5/1.8/2.5/3.3 V per driver |
| Package | 24-pin QFN, 4 × 4 mm, 0.5 mm pitch, exposed thermal pad |
Pinout & Package
SI5338N-B09663-GMR uses a 24-lead QFN package (4 × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin assignments are standardized across Si5338 family variants and validated per Skyworks Rev. 1.6 datasheet.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN1, IN2 | Differential input clock 1 | Accepts 5–710 MHz AC-coupled differential reference; internal 100 Ω termination enabled |
| IN3, IN4 | Single-ended input clock 2 | Supports 5–200 MHz CMOS-level input; VIH = 0.7×VDD, VIL = 0.3×VDD |
| CLK0A, CLK0B | Differential output 0 | Configurable as LVPECL/LVDS/HCSL/CML; independent voltage (VDDO0) and format |
| CLK1A, CLK1B | Differential output 1 | Independent MultiSynth™ channel; supports phase offset <20 ps step resolution |
| CLK2A, CLK2B | Differential output 2 | Programmable spread spectrum (0.5–5.0% spread, 33–63 kHz rate) |
| CLK3A, CLK3B | Differential output 3 | Loss-of-lock and loss-of-signal alarm reporting via INTR pin |
| SCL, SDA | I²C interface | Standard-mode (100 kHz) and fast-mode (400 kHz) compatible; SMBus Level 2 compliant |
| INTR | Interrupt output | Open-drain status indicator for LOS, LOL, or configuration-complete events |
| VDD, VDDO0–VDDO3 | Power supplies | VDD = core supply (1.8/2.5/3.3 V); VDDOx = independent output buffer supply per channel |
| GND, RSVD_GND | Ground connections | Multiple GND pins and reserved ground pad ensure low-noise return paths and thermal dissipation |
Key Features
| Feature | Design Value |
|---|---|
| MultiSynth™ synthesis | Four independent fractional-N synthesizers enable any-frequency generation (0.16–710 MHz) with 1 ppb resolution and zero ppm error |
| PCIe Gen 4 compliance | 0.15–0.45 ps RMS jitter in common clock mode satisfies PCIe Base Spec 4.0 rev. 0.5 requirements |
| Flexible output configuration | Each of four output pairs supports independent signal format (LVDS/LVPECL/HCSL/CMOS), voltage (1.5–3.3 V), and termination |
| Glitchless frequency tuning | Pin-controlled or I²C-based frequency increment/decrement in 1 ppm steps without output interruption |
| Programmable phase alignment | ±45 ns initial phase offset and <20 ps step resolution per output for precise inter-channel skew control |
| Spread spectrum capability | Configurable on any output: 0.5–5.0% down-spread, 33–63 kHz modulation rate, no external components required |
Applications
| PCIe Gen 4 Switch Timing | Ethernet Switch/Routing |
|---|---|
Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe Gen 4 switch ASICs in a data center fabric card. IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent, low-jitter (≤0.45 ps RMS) 100 MHz HCSL clocks with matched phase alignment. Use Value: Eliminates need for four discrete oscillators; ensures PCIe Gen 4 common clock compliance and reduces board area by 65% vs. discrete solution. |
Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10/25 GbE PHYs and packet processors in a carrier-grade Ethernet switch. IC Role / Device Role / Timing Role: Any-frequency synthesizer producing three precise frequencies from a single 25 MHz crystal reference. Use Value: Enables single-reference design with zero ppm accuracy on all outputs, reducing BOM count and improving long-term frequency stability. |
| Broadcast Video Timing | FPGA/Processor Clocking |
Use Scenario: Delivering SMPTE ST 2082 (27 Gbps) and ST 2081 (12 Gbps) reference clocks to video serializer/deserializer ICs in 4K/8K broadcast equipment. IC Role / Device Role / Timing Role: High-frequency clock generator supporting 27 GHz-derived rates (e.g., 297 MHz, 594 MHz) with sub-ps jitter performance. Use Value: Meets SMPTE jitter limits (<0.5 ps RMS) for UHD video transport; eliminates jitter accumulation from cascaded PLLs. |
Use Scenario: Supplying core, memory, and I/O clocks to Xilinx Versal or Intel Agilex FPGAs in adaptive compute acceleration platforms. IC Role / Device Role / Timing Role: Configurable quad clock source generating 300 MHz (core), 1600 MHz DDR4, 100 MHz PCIe, and 25 MHz debug clocks simultaneously. Use Value: Reduces FPGA pin count and PCB routing complexity; supports dynamic voltage/frequency scaling via I²C reprogramming. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad-output clock generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5332A-D08889-GM | Higher integration: 8 outputs, dual-loop architecture, lower jitter (0.35 ps RMS), supports JESD204B deterministic latency | Targeted at JESD204B-compliant ADC/DAC systems and multi-ASIC synchronization requiring sub-100 ps skew | Choose when >4 outputs, tighter jitter, or deterministic latency are required; higher cost and larger 5 × 5 mm package |
| ICS8430I-01T | Fixed-frequency quad LVDS generator (no I²C programming); 1.2 ps RMS jitter; 3.3 V only; no spread spectrum or phase control | Cost-sensitive, static-clock applications where frequency agility and advanced features are unnecessary | Choose for simple, low-cost replacement of legacy fixed-frequency oscillators; not suitable for PCIe Gen 4 or reconfigurable systems |
Compared with Si5332A-D08889-GM and ICS8430I-01T, SI5338N-B09663-GMR delivers optimal balance of programmability, PCIe Gen 4 compliance, and compact 4 × 4 mm footprint - making it ideal for space-constrained, multi-standard timing designs requiring field-upgradable clock trees.
Availability
SI5338N-B09663-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, Ethernet switching infrastructure, and broadcast video equipment requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.
Supply support for SI5338N-B09663-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for communications, automotive, and industrial markets.
The Si5338 product line was designed to replace multiple discrete oscillators with a single, software-configurable clock generator for high-speed serial interfaces - targeting PCIe, Ethernet, and broadcast video timing applications demanding ultra-low jitter and flexible frequency synthesis.
FAQ
What is the maximum output frequency supported by SI5338N-B09663-GMR in LVPECL mode?
The SI5338N-B09663-GMR supports LVPECL output frequencies up to 710 MHz, as specified in Table 6 of the Skyworks datasheet. This applies when using differential outputs with appropriate termination and layout practices to maintain signal integrity and jitter performance.
Does SI5338N-B09663-GMR support PCIe Gen 4 Separate Reference No Spread (SRNS) mode?
Yes, SI5338N-B09663-GMR is compliant with PCIe Gen 4 SRNS requirements, delivering ≤0.32 ps RMS jitter under specified test conditions (PLL BW 2–4 MHz, CDR = 10 MHz), as documented in Table 12 of the Skyworks Rev. 1.6 datasheet.
Can SI5338N-B09663-GMR generate four different output frequencies simultaneously?
Yes, SI5338N-B09663-GMR uses four independent MultiSynth™ engines to synthesize four distinct output frequencies simultaneously - each configurable from 0.16 MHz up to device-specific maximums (e.g., 710 MHz for LVPECL), with zero ppm error and 1 ppb resolution.
What input reference options does SI5338N-B09663-GMR support?
SI5338N-B09663-GMR accepts multiple reference types: 8–30 MHz fundamental-mode crystal, 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL, or 5–710 MHz differential (LVDS/LVPECL/HCSL) inputs - enabling flexible system-level clock tree design.
Is ClockBuilder Pro software required to configure SI5338N-B09663-GMR?
No - ClockBuilder Pro is optional but strongly recommended for SI5338N-B09663-GMR configuration. The device supports direct I²C register writes; however, ClockBuilder Pro automates register calculation, validates jitter/performance, and generates production-ready configuration files for reliable deployment.
SI5338N-B09663-GMR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- *
- Package/Case:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- PLL:
- -
- Main Purpose:
- -
- Input:
- -
- Output:
- -
- Number of Circuits:
- -
- Ratio - Input:Output:
- -
- Differential - Input:Output:
- -
- Frequency - Max:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Mounting Type:
- -
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- -
SI5338N-B09663-GMR FAQ
1.How can I place an order for SI5338N-B09663-GMR through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5338N-B09663-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5338N-B09663-GMR reliable?
The price and inventory of SI5338N-B09663-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338N-B09663-GMR is usually 5 days.
3.What payment methods are accepted for SI5338N-B09663-GMR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338N-B09663-GMR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5338N-B09663-GMR?
SI5338N-B09663-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5338N-B09663-GMR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5338N-B09663-GMR?
For technical support, including SI5338N-B09663-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338N-B09663-GMR requirements.
6.How does Aetrix verify that SI5338N-B09663-GMR is sourced from the original manufacturer or authorized distributors?
All SI5338N-B09663-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338N-B09663-GMR meets industry standards.
7.What is the process for return or replacement of SI5338N-B09663-GMR?
All SI5338N-B09663-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338N-B09663-GMR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5338N-B09663-GMR part is unused and in its original packaging.
Return procedure for SI5338N-B09663-GMR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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