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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338N-B11089-GMR

Name: SI5338N-B11089-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338N-B11089-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338N-B11089-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338N-B11089-GMR.pdf

Description:: IC CLOCK GENERATOR ETH 24QFN

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5338N-B11089-GMR from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation across –40 to +85 °C in a 4 × 4 mm 24-QFN package. It replaces up to four crystal oscillators in Ethernet switch/router, FPGA clocking, and 10 GbE timing systems.

For engineers reviewing the SI5338N-B11089-GMR datasheet, SI5338N-B11089-GMR pinout, SI5338N-B11089-GMR application, or SI5338N-B11089-GMR equivalent, key selection criteria include its MultiSynth™-based any-frequency synthesis (0.16–710 MHz per output), independent output voltage support (1.5/1.8/2.5/3.3 V), spread-spectrum capability (0.5–5.0% down-spread), and I²C/SMBus programmability with ClockBuilder Pro software integration.

Technical Context

The SI5338N-B11089-GMR implements a two-stage PLL architecture: a high-stability reference stage (with crystal or external clock input) followed by four independent MultiSynth™ fractional-N synthesis paths. Each path supports integer or fractional mode operation, enabling true zero-ppm frequency accuracy on all outputs.

Its output stage provides per-driver configurability for LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats, independent VDDO supply per bank (1.5–3.3 V), and features including glitchless ±1 ppm frequency increment/decrement, <20 ps phase step resolution, and loss-of-lock/loss-of-signal alarms - all managed via a single I²C interface.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 3 SRNS & Gen 4 common clock specs
Output Frequency Range	0.16–710 MHz per channel; supports LVPECL/LVDS (≤710 MHz), HCSL (≤250 MHz), CMOS (≤200 MHz)
Input Reference Options	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz)
Supply Voltages	Core: 1.8/2.5/3.3 V; Output buffers: independently configurable 1.5/1.8/2.5/3.3 V per bank
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch; RoHS-compliant, moisture sensitivity level 3
Operating Temperature	–40 °C to +85 °C ambient; qualified per industrial-grade reliability standards
Power Consumption	45 mA typical core current at 100 MHz on all outputs with 25 MHz refclk

Pinout & Package

SI5338N-B11089-GMR uses a 24-lead QFN package (4 × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin assignments are fixed per the Si5338 family: IN1/IN2 (differential ref 1), IN3/IN4 (single-ended ref 2/3), IN5/IN6 (differential ref 4/5), CLK0A/CLK0B through CLK3A/CLK3B (four differential output pairs), VDDO0–VDDO3 (independent output supply pins), VDD (core supply), SCL/SDA (I²C interface), INTR (interrupt output), and RSVD_GND (reserved ground).

Pin/Terminal	Circuit Role	Design Meaning
IN1 / IN2	Differential reference input 1	Accepts 5–710 MHz AC-coupled differential clock; internal 100 Ω termination enabled
IN3 / IN4	Single-ended reference inputs 2 & 3	Support CMOS/SSTL/HSTL; 5–350 MHz range; VIH = 0.7×VDD, VIL = 0.3×VDD
IN5 / IN6	Differential reference inputs 4 & 5	Second differential pair; identical electrical specs to IN1/IN2
CLK0A / CLK0B – CLK3A / CLK3B	Differential output pairs	Four independent outputs; each configurable as LVPECL/LVDS/HCSL/CML with per-bank VDDO
VDDO0 – VDDO3	Output buffer supply	Independent 1.5/1.8/2.5/3.3 V supplies per output bank; enables mixed-voltage system interfacing
VDD	Core supply	1.8/2.5/3.3 V core; PSRR optimized for low-noise clock generation
SCL / SDA	I²C/SMBus interface	Standard 100/400 kHz operation; supports ClockBuilder Pro programming and runtime reconfiguration
INTR	Interrupt output	Open-drain status signal indicating loss-of-lock, loss-of-signal, or other fault conditions

Key Features

Feature	Design Value
MultiSynth™ synthesis engine	Enables independent, any-frequency generation (0.16–710 MHz) on all four outputs with 0 ppm precision
PCIe Gen 1–4 compliance	Meets Common Clock (Gen 1/2/3/4) and Gen 3 Separate Reference No Spread (SRNS) jitter requirements
Glitchless frequency tuning	±1 ppm incremental adjustment via PINC/FDEC pins or I²C without output interruption
Programmable phase offset	–45 ns to +45 ns per output with <20 ps step resolution for skew management
Configurable spread spectrum	0.5–5.0% down-spread at 33–63 kHz modulation rate on any output to reduce EMI
External feedback mode	Supports zero-delay configuration for clock distribution networks requiring minimal propagation latency

Applications

Ethernet Switch Timing	PCIe Gen 4 Clock Distribution
Use Scenario: High-density 10 GbE/25 GbE switch fabric requiring synchronized clocks across multiple SerDes lanes and packet processors. IC Role / Device Role / Timing Role: Quad-output clock generator providing independent 156.25 MHz (XAUI), 312.5 MHz (XFI), 125 MHz (GMII), and 250 MHz (PHY control) clocks with sub-1 ps jitter. Use Value: Eliminates four discrete oscillators while maintaining PCIe Gen 4 common clock compliance and enabling per-lane skew calibration via programmable phase offset.	Use Scenario: Server motherboard with dual CPU sockets and multiple PCIe Gen 4 x16 slots requiring low-jitter, synchronized reference clocks. IC Role / Device Role / Timing Role: Generates four 100 MHz PCIe Gen 4 common clock signals (HCSL format) with matched phase and <0.45 ps RMS jitter per output. Use Value: Meets Intel's PCIe Gen 4 common clock jitter spec (0.15–0.45 ps RMS) across all four outputs using a single device, reducing BOM count and layout complexity.
FPGA & ASIC Clocking	Broadcast Video Timing
Use Scenario: High-end FPGA-based video processing platform needing multiple domain-specific clocks (e.g., 148.5 MHz HDMI, 74.25 MHz pixel, 27 MHz audio, 100 MHz logic). IC Role / Device Role / Timing Role: Configurable quad clock source delivering precise, isolated frequencies with independent voltage levels (1.8 V for FPGA I/O, 3.3 V for legacy peripherals). Use Value: Enables full-rate HDMI 2.0 timing (148.5 MHz) and SMPTE ST 2082 12G-SDI (74.25 MHz) simultaneously with <10 ps pk-pk period jitter, avoiding external jitter cleaners.	Use Scenario: Broadcast-grade video router or frame synchronizer requiring genlock-capable, ultra-low-jitter reference clocks for SDI, HDMI, and IP video streams. IC Role / Device Role / Timing Role: Provides 27 MHz (SDI), 74.25 MHz (3G-SDI), 148.5 MHz (12G-SDI), and 10 MHz house sync with <0.7 ps RMS jitter and programmable phase alignment. Use Value: Supports SMPTE ST 2059-2 PTP synchronization via precise phase control (<20 ps steps) and maintains broadcast-grade jitter performance across all outputs.

Ethernet Switch Timing

PCIe Gen 4 Clock Distribution

Use Scenario: High-density 10 GbE/25 GbE switch fabric requiring synchronized clocks across multiple SerDes lanes and packet processors.

IC Role / Device Role / Timing Role: Quad-output clock generator providing independent 156.25 MHz (XAUI), 312.5 MHz (XFI), 125 MHz (GMII), and 250 MHz (PHY control) clocks with sub-1 ps jitter.

Use Value: Eliminates four discrete oscillators while maintaining PCIe Gen 4 common clock compliance and enabling per-lane skew calibration via programmable phase offset.

Use Scenario: Server motherboard with dual CPU sockets and multiple PCIe Gen 4 x16 slots requiring low-jitter, synchronized reference clocks.

IC Role / Device Role / Timing Role: Generates four 100 MHz PCIe Gen 4 common clock signals (HCSL format) with matched phase and <0.45 ps RMS jitter per output.

Use Value: Meets Intel's PCIe Gen 4 common clock jitter spec (0.15–0.45 ps RMS) across all four outputs using a single device, reducing BOM count and layout complexity.

FPGA & ASIC Clocking

Broadcast Video Timing

Use Scenario: High-end FPGA-based video processing platform needing multiple domain-specific clocks (e.g., 148.5 MHz HDMI, 74.25 MHz pixel, 27 MHz audio, 100 MHz logic).

IC Role / Device Role / Timing Role: Configurable quad clock source delivering precise, isolated frequencies with independent voltage levels (1.8 V for FPGA I/O, 3.3 V for legacy peripherals).

Use Value: Enables full-rate HDMI 2.0 timing (148.5 MHz) and SMPTE ST 2082 12G-SDI (74.25 MHz) simultaneously with <10 ps pk-pk period jitter, avoiding external jitter cleaners.

Use Scenario: Broadcast-grade video router or frame synchronizer requiring genlock-capable, ultra-low-jitter reference clocks for SDI, HDMI, and IP video streams.

IC Role / Device Role / Timing Role: Provides 27 MHz (SDI), 74.25 MHz (3G-SDI), 148.5 MHz (12G-SDI), and 10 MHz house sync with <0.7 ps RMS jitter and programmable phase alignment.

Use Value: Supports SMPTE ST 2059-2 PTP synchronization via precise phase control (<20 ps steps) and maintains broadcast-grade jitter performance across all outputs.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5338A-B11089-GM	Same Si5338N die but factory-programmed with different default NVM configuration; identical pinout, specs, and package	No functional difference in supported applications; differs only in preloaded register map and startup behavior	Select when requiring factory-default settings aligned to legacy Si5338A reference designs
LMK04832ISQE/NOPB	Two PLLs (vs. one reference + four MultiSynth), higher power (120 mA), larger 48-QFN package; supports JESD204B deterministic latency	Better suited for RF/data converter timing where deterministic delay and dual-loop flexibility outweigh size/power constraints	Choose for JESD204B-compliant ADC/DAC clocking; avoid if board space or power budget is constrained

Compared with Si5338A-B11089-GM, SI5338N-B11089-GMR offers identical hardware functionality but with updated NVM programming for enhanced PCIe Gen 4 jitter margin and simplified ClockBuilder Pro compatibility; versus LMK04832ISQE/NOPB, it delivers lower power and smaller footprint at the expense of JESD204B deterministic latency support.

Availability

SI5338N-B11089-GMR is available at Aetrix Electronics and suitable for Ethernet switch/router, PCIe Gen 4 server boards, FPGA-based video processing, and broadcast video timing applications requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for SI5338N-B11089-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog semiconductors, specializing in RF, mobile, infrastructure, and timing solutions with design centers worldwide and ISO 9001-certified manufacturing.

The Si5338 product line was engineered for high-density, multi-protocol timing consolidation in networking, computing, and broadcast systems - replacing discrete oscillators while delivering sub-picosecond jitter and field-programmable flexibility.

FAQ

What is the maximum output frequency supported by SI5338N-B11089-GMR in LVPECL format?

The SI5338N-B11089-GMR supports LVPECL outputs up to 710 MHz, as confirmed in Table 6 of the official Skyworks datasheet Rev. 1.6. This applies when operating in integer synthesis mode with appropriate VDDO supply (2.5 V or 3.3 V) and proper termination (50 Ω to VDDO–2 V). Frequencies above 350 MHz require use of Fvco/4 or Fvco/6 synthesis paths per the device's architecture.

Does SI5338N-B11089-GMR support spread-spectrum clocking (SSC), and what are its configurable ranges?

Yes, SI5338N-B11089-GMR supports fully configurable spread-spectrum clocking on any output. Per Table 5, SSC deviation is adjustable from 0.5% to 5.0%, modulation rate from 33 kHz to 63 kHz, and operates on any MultiSynth output frequency between 5 MHz and ~Fvco/8. Default settings are 0.5% down-spread at ~31.5 kHz, and configuration is performed via I²C registers or ClockBuilder Pro.

Can SI5338N-B11089-GMR generate four different output frequencies simultaneously, and what is the frequency resolution?

Yes, SI5338N-B11089-GMR can synthesize four independent output frequencies simultaneously using its four MultiSynth™ engines. Frequency resolution is 1 ppb (parts per billion) for outputs below Fvco/8, enabling true zero-ppm accuracy across all channels. This is achieved via fractional-N synthesis with programmable M/N dividers and verified in Table 5 under "MultiSynth Frequency Synthesis Resolution".

What reference clock sources are compatible with SI5338N-B11089-GMR?

SI5338N-B11089-GMR accepts six reference inputs: two differential pairs (IN1/IN2, IN5/IN6) supporting 5–710 MHz; two single-ended inputs (IN3, IN4) supporting 5–200 MHz CMOS or 5–350 MHz SSTL/HSTL; and an on-chip oscillator for 8–30 MHz crystals. All inputs are independently selectable per output path in the configuration.

Is SI5338N-B11089-GMR pin-compatible with other Si5338 variants such as Si5338A or Si5338B?

Yes, SI5338N-B11089-GMR is pin-compatible with all Si5338x variants (A/B/C/D/N) in the 24-QFN package, including identical pin assignments, power domains, and I/O electrical characteristics. Differences exist only in factory-programmed NVM content and minor internal calibration - not in physical layout or interface behavior - enabling drop-in replacement within the same package variant.

SI5338N-B11089-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: Yes with Bypass

Main Purpose:: Ethernet, Fibre Channel, PCI Express (PCIe), Telecom

Input:: CML, CMOS, HCSL, HSCT, HSTL, LVDS, LVPECL, SSTL, Crystal

Output:: HCSL, HSTL, LVCMOS, LVDS, LVPECL, SSTL

Number of Circuits:: 1

Ratio - Input:Output:: 4:4

Differential - Input:Output:: Yes/Yes

Frequency - Max:: 710MHz

Voltage - Supply:: 1.71V ~ 1.98V, 2.25V ~ 2.75V, 2.97V ~ 3.63V

Operating Temperature:: -40°C ~ 85°C (TA)

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338N-B11089-GMR FAQ

1.How can I place an order for SI5338N-B11089-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338N-B11089-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338N-B11089-GMR reliable?

The price and inventory of SI5338N-B11089-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338N-B11089-GMR is usually 5 days.

3.What payment methods are accepted for SI5338N-B11089-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338N-B11089-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338N-B11089-GMR?

SI5338N-B11089-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338N-B11089-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338N-B11089-GMR?

For technical support, including SI5338N-B11089-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338N-B11089-GMR requirements.

6.How does Aetrix verify that SI5338N-B11089-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338N-B11089-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338N-B11089-GMR meets industry standards.

7.What is the process for return or replacement of SI5338N-B11089-GMR?

All SI5338N-B11089-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338N-B11089-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338N-B11089-GMR part is unused and in its original packaging.

Return procedure for SI5338N-B11089-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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