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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338P-B04154-GMR

Name: SI5338P-B04154-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338P-B04154-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338P-B04154-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338P-B04154-GMR.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5338P-B04154-GMR from Skyworks Solutions is a quad-output, I²C-programmable clock generator implementing MultiSynth™ frequency synthesis with 0 ppm precision per output, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and support for LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL output formats across 0.16–710 MHz. It replaces up to four crystal oscillators in FPGA, processor, and Ethernet switch timing systems.

For engineers reviewing the SI5338P-B04154-GMR datasheet, SI5338P-B04154-GMR pinout, SI5338P-B04154-GMR application, or SI5338P-B04154-GMR equivalent, key selection criteria include differential output jitter performance at 125 MHz (0.7 ps RMS), independent per-output voltage configuration (1.5/1.8/2.5/3.3 V), 24-pin QFN package footprint, and I²C/SMBus programmability with ClockBuilder Pro software support.

Technical Context

The SI5338P-B04154-GMR integrates a high-stability PLL-based synthesis stage followed by four independent MultiSynth™ fractional-N dividers, enabling simultaneous generation of four unrelated frequencies with integer or fractional mode operation. Each output driver supports format- and voltage-selectable termination with configurable slew rate and drive strength.

It accepts six input references - including 8–30 MHz crystals, 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL, and 5–710 MHz differential signals - and provides loss-of-lock and loss-of-signal alarms, external feedback for zero-delay mode, and independent ±45 ns programmable phase offset per output with <20 ps step resolution.

Key Specifications

Parameter	Value and Actual Design Meaning
Output Count	Four independent differential or single-ended outputs (CLK0A/B through CLK3A/B)
Phase Jitter (RMS)	0.7 ps typical over 12 kHz–20 MHz; meets PCIe Gen 3 SRNS and GbE jitter requirements
Frequency Range	0.16–710 MHz per output; supports LVPECL/LVDS up to 710 MHz, HCSL up to 250 MHz, CMOS up to 200 MHz
Input Reference	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz)
Supply Voltages	Core: 1.8/2.5/3.3 V; Output buffers: independently configurable 1.5/1.8/2.5/3.3 V per driver
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch, exposed thermal pad
Operating Temp	–40 °C to +85 °C ambient; qualified for industrial and telecom line card environments

Pinout & Package

SI5338P-B04154-GMR uses a 24-pin QFN package (4 × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin assignments are fixed per the Si5338 family and validated in Skyworks Rev. 1.6 datasheet Figure 1 (Top View).

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2	Differential reference input pair	Accepts 5–710 MHz AC-coupled differential clocks; requires external 100 Ω termination
IN3, IN4	Single-ended reference inputs	Support CMOS/SSTL/HSTL signals from 5–350 MHz; internal 20 kΩ pull-up/pull-down selectable
CLK0A, CLK0B – CLK3A, CLK3B	Differential clock outputs	Four independent pairs; each configurable as LVPECL/LVDS/HCSL/CML with per-output VDDO supply
VDDO0–VDDO3	Output buffer supply rails	Independent 1.5/1.8/2.5/3.3 V supplies per output bank; enables mixed-voltage system interfacing
SCL, SDA	I²C/SMBus programming interface	Standard two-wire serial bus; supports ClockBuilder Pro configuration and runtime frequency adjustment
INTR	Interrupt output	Open-drain status indicator for loss-of-lock, loss-of-signal, or PLL unlock events
VDD	Core supply	Single 1.8/2.5/3.3 V core rail; delivers 45 mA typical current at 100 MHz output load
GND, RSVD_GND	Ground connections	Multiple dedicated ground pins and reserved ground pad ensure low-noise power integrity and thermal dissipation

Key Features

Feature	Design Value
MultiSynth™ synthesis	Enables true zero-ppm frequency accuracy on all four outputs without external VCXOs or trimming components
Independent output voltage control	Each of four output banks powered separately (1.5/1.8/2.5/3.3 V), eliminating level-shifter ICs in mixed-voltage designs
Glitchless frequency tuning	1 ppm step size via PINC/FDEC pins or I²C; no output interruption during real-time clock rate changes
Programmable phase offset	±45 ns range per output with <20 ps resolution, enabling precise skew alignment in multi-lane SerDes or memory interfaces
Spread spectrum capability	Configurable 0.5–5.0% down-spread at 33–63 kHz on any output to reduce EMI in dense PCB layouts
PCIe Gen 4 compliance	Validated 0.15–0.45 ps RMS jitter in Common Clock mode per PCI-SIG Base Spec 4.0 rev. 0.5

Applications

PCIe Gen 3/4 Switch Timing	Ethernet Switch/Routing
Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe Gen 3/4 switches and endpoint devices in a server backplane. IC Role / Device Role / Timing Role: Quad-output clock generator delivering Common Clock architecture-compliant timing with SRNS validation. Use Value: Eliminates four discrete oscillators while meeting 0.32 ps RMS jitter requirement for PCIe Gen 3 Separate Reference No Spread mode.	Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10 GbE PHYs, packet processors, and switch fabric ASICs. IC Role / Device Role / Timing Role: Any-frequency synthesizer supporting IEEE 802.3 standards with low additive jitter in buffer mode. Use Value: Achieves 0.7 ps RMS random jitter at 125 MHz, satisfying GbE 12 kHz–20 MHz mask requirements without external filtering.
FPGA & Processor Clocking	Broadcast Video Timing
Use Scenario: Supplying multiple asynchronous clocks (e.g., 100 MHz AXI, 200 MHz DDR, 300 MHz video subsystem) to Xilinx Versal or Intel Agilex FPGAs. IC Role / Device Role / Timing Role: Configurable quad clock source with independent format and voltage per output bank. Use Value: Enables direct LVDS-to-FPGA and HCSL-to-memory interface without level shifters or discrete buffers.	Use Scenario: Delivering SMPTE ST 2082 (12G-SDI) 742.5 MHz and ST 2081 (6G-SDI) 371.25 MHz clocks with sub-1 ps jitter to video encoder/decoder SoCs. IC Role / Device Role / Timing Role: High-frequency differential clock generator operating in LVPECL mode above 350 MHz. Use Value: Supports dual-frequency output above 350 MHz (Fvco/4 and Fvco/6) required for multi-rate broadcast infrastructure.

PCIe Gen 3/4 Switch Timing

Ethernet Switch/Routing

Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe Gen 3/4 switches and endpoint devices in a server backplane.

IC Role / Device Role / Timing Role: Quad-output clock generator delivering Common Clock architecture-compliant timing with SRNS validation.

Use Value: Eliminates four discrete oscillators while meeting 0.32 ps RMS jitter requirement for PCIe Gen 3 Separate Reference No Spread mode.

Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10 GbE PHYs, packet processors, and switch fabric ASICs.

IC Role / Device Role / Timing Role: Any-frequency synthesizer supporting IEEE 802.3 standards with low additive jitter in buffer mode.

Use Value: Achieves 0.7 ps RMS random jitter at 125 MHz, satisfying GbE 12 kHz–20 MHz mask requirements without external filtering.

FPGA & Processor Clocking

Broadcast Video Timing

Use Scenario: Supplying multiple asynchronous clocks (e.g., 100 MHz AXI, 200 MHz DDR, 300 MHz video subsystem) to Xilinx Versal or Intel Agilex FPGAs.

IC Role / Device Role / Timing Role: Configurable quad clock source with independent format and voltage per output bank.

Use Value: Enables direct LVDS-to-FPGA and HCSL-to-memory interface without level shifters or discrete buffers.

Use Scenario: Delivering SMPTE ST 2082 (12G-SDI) 742.5 MHz and ST 2081 (6G-SDI) 371.25 MHz clocks with sub-1 ps jitter to video encoder/decoder SoCs.

IC Role / Device Role / Timing Role: High-frequency differential clock generator operating in LVPECL mode above 350 MHz.

Use Value: Supports dual-frequency output above 350 MHz (Fvco/4 and Fvco/6) required for multi-rate broadcast infrastructure.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D06154-GM	Higher integration: includes integrated crystal, lower jitter (0.35 ps RMS), but limited to three outputs and no spread spectrum	Best suited for space-constrained, ultra-low-jitter applications where only three clocks are needed and EMI reduction is not required	Select when board area and jitter are prioritized over output count and SSC flexibility
ICS854S01IAGLF	Fixed-frequency, non-programmable quad LVDS generator; 1.2 ps RMS jitter; no I²C interface or voltage configurability	Applicable only in stable, unchanging clock tree designs requiring minimal BOM count and no runtime reconfiguration	Select only if design requires no field updates, no mixed-voltage outputs, and fixed 100/125/156.25 MHz frequencies

Compared with Si5332A-D06154-GM and ICS854S01IAGLF, SI5338P-B04154-GMR uniquely balances full I²C programmability, four independent outputs, spread spectrum support, and PCIe Gen 4 compliance - making it optimal for evolving, multi-standard timing architectures requiring post-silicon tuning.

Availability

SI5338P-B04154-GMR is available at Aetrix Electronics and suitable for PCIe switch timing, Ethernet routing, FPGA clocking, and broadcast video applications requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for SI5338P-B04154-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5338 product line was designed for high-performance, software-configurable clock generation in multi-protocol systems - targeting PCIe, Ethernet, Fibre Channel, and broadcast video platforms needing flexible, low-jitter timing with minimal board space.

FAQ

What is the maximum output frequency supported by SI5338P-B04154-GMR in LVPECL mode?

The SI5338P-B04154-GMR supports up to 710 MHz in LVPECL mode per output, as specified in Table 6 of the Skyworks Rev. 1.6 datasheet. This capability enables direct clocking of high-speed SerDes lanes in PCIe Gen 4 and 10G/25G Ethernet applications without external frequency multiplication.

Does SI5338P-B04154-GMR require an external crystal, or can it use other reference sources?

SI5338P-B04154-GMR supports multiple reference inputs: an 8–30 MHz crystal (on IN1/IN2), a 5–200 MHz CMOS signal (on IN3/IN4), or differential clocks up to 710 MHz (on IN1/IN2, IN5/IN6). No external crystal is mandatory - the device operates with any of these sources, offering design flexibility in reference architecture.

How is SI5338P-B04154-GMR programmed, and what tools are required?

SI5338P-B04154-GMR is programmed via its I²C/SMBus interface using Skyworks' ClockBuilder Pro software. The tool generates configuration files, validates timing constraints, and supports in-system programming - eliminating need for custom firmware. SI5338P-B04154-GMR also supports pin-controlled frequency increment/decrement for runtime tuning without host intervention.

What jitter performance does SI5338P-B04154-GMR deliver for PCIe Gen 4 applications?

SI5338P-B04154-GMR delivers 0.15–0.45 ps RMS jitter in PCIe Gen 4 Common Clock mode (per PCI-SIG Base Spec 4.0 rev. 0.5), measured at 100 MHz HCSL output with PLL bandwidth set to 2–4 MHz and CDR at 10 MHz - fully compliant for root complex and endpoint timing.

Can SI5338P-B04154-GMR generate different output voltages simultaneously on its four outputs?

Yes. SI5338P-B04154-GMR provides independent VDDO0–VDDO3 supply pins, allowing each of its four output banks to be powered at 1.5 V, 1.8 V, 2.5 V, or 3.3 V concurrently. This enables direct interfacing with mixed-voltage ASICs, FPGAs, and PHYs without external level translators.

SI5338P-B04154-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338P-B04154-GMR FAQ

1.How can I place an order for SI5338P-B04154-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338P-B04154-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338P-B04154-GMR reliable?

The price and inventory of SI5338P-B04154-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338P-B04154-GMR is usually 5 days.

3.What payment methods are accepted for SI5338P-B04154-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338P-B04154-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338P-B04154-GMR?

SI5338P-B04154-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338P-B04154-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338P-B04154-GMR?

For technical support, including SI5338P-B04154-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338P-B04154-GMR requirements.

6.How does Aetrix verify that SI5338P-B04154-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338P-B04154-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338P-B04154-GMR meets industry standards.

7.What is the process for return or replacement of SI5338P-B04154-GMR?

All SI5338P-B04154-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338P-B04154-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338P-B04154-GMR part is unused and in its original packaging.

Return procedure for SI5338P-B04154-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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