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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338P-B04725-GM

Name: SI5338P-B04725-GM
Brand: Skyworks Solutions Inc.
SKU: SI5338P-B04725-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338P-B04725-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338P-B04725-GM.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5338P-B04725-GM from Skyworks Solutions is a quad-output, I²C-programmable clock generator with MultiSynth™ frequency synthesis, delivering 0 ppm precision on all four outputs, <0.7 ps RMS phase jitter (typ), PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and support for LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL output formats across 0.16–710 MHz. It replaces up to four crystal oscillators in high-speed serial interface timing applications.

For engineers reviewing the SI5338P-B04725-GM datasheet, SI5338P-B04725-GM pinout, SI5338P-B04725-GM application, or SI5338P-B04725-GM equivalent, key selection criteria include its 4× differential output capability, independent per-output voltage control (1.5/1.8/2.5/3.3 V), 24-pin 4×4 mm QFN package, I²C/SMBus programmability, and PCIe Gen 4 jitter compliance at 0.15–0.45 ps RMS.

Technical Context

The SI5338P-B04725-GM implements a two-stage PLL architecture: a high-stability reference stage followed by four independent MultiSynth™ fractional-N synthesizers, each driving one output pair. Its input flexibility supports crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), and differential (5–710 MHz) references.

Each output driver is independently configurable for format, voltage, spread-spectrum modulation (0.5–5.0% spread, 33–63 kHz rate), phase offset (±45 ns, <20 ps step), and frequency increment/decrement (1 ppm steps, glitchless). The device operates from a single 1.8/2.5/3.3 V core supply with 45 mA typical current draw and –40 to +85 °C industrial temperature range.

Key Specifications

Parameter	Value and Actual Design Meaning
Output Count & Type	Four differential output pairs (CLK0A/B through CLK3A/B), supporting up to eight single-ended clocks or mixed configurations
Phase Jitter (RMS)	0.7 ps typ (12 kHz–20 MHz), meeting PCIe Gen 4 common clock and Gen 3 SRNS requirements
Frequency Range	0.16–710 MHz per output, with integer/fractional synthesis and true zero-ppm accuracy
Input Reference Support	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz)
Supply Voltages	Core: 1.8/2.5/3.3 V ±10%; Output buffers: independently selectable 1.5/1.8/2.5/3.3 V per driver
Package	24-pin QFN, 4 mm × 4 mm, 0.5 mm pitch, exposed thermal pad
Operating Temperature	–40 °C to +85 °C, qualified for industrial embedded and telecom line card environments

Pinout & Package

SI5338P-B04725-GM uses a 24-pin, 4 mm × 4 mm QFN package with exposed thermal pad (pin 24 = GND). Pin functions are defined per Skyworks Rev. 1.6 datasheet, with dedicated differential inputs (IN1/IN2, IN5/IN6), single-ended inputs (IN3, IN4), four differential output pairs (CLK0A/B through CLK3A/B), I²C interface (SCL/SDA), interrupt (INTR), power (VDD, VDDO0–VDDO3), and reserved ground (RSVD_GND).

Pin/Terminal	Circuit Role	Design Meaning
IN1 / IN2	Differential Input Pair 1	Accepts 5–710 MHz AC-coupled differential clock; requires external 100 Ω termination
IN5 / IN6	Differential Input Pair 2	Second 5–710 MHz differential reference input, enabling dual-reference redundancy or frequency translation
IN3 / IN4	Single-Ended Inputs	Support 5–200 MHz CMOS-level clocks; internal 20 kΩ pull-up/pull-down enables flexible logic level detection
CLK0A / CLK0B through CLK3A / CLK3B	Differential Output Pairs	Four independent, format-configurable outputs (LVPECL/LVDS/HCSL/CML/SSTL/HSTL/CMOS)
VDDO0–VDDO3	Output Buffer Supplies	Independent 1.5/1.8/2.5/3.3 V supplies per output bank-enables mixed-voltage system interfacing
SCL / SDA	I²C/SMBus Interface	Standard 100/400 kHz operation; supports ClockBuilder Pro configuration and runtime reprogramming
INTR	Interrupt Output	Open-drain status signal indicating loss-of-lock (LOL) or loss-of-signal (LOS) events

Key Features

Feature	Design Value
MultiSynth™ Synthesis	Four independent fractional-N synthesizers enable any-frequency generation (0.16–710 MHz) with 0 ppm error on all outputs
PCIe Gen 4 Compliance	0.15–0.45 ps RMS jitter (10 kHz–50 MHz) meets PCIe Base Spec 4.0 common clock requirements
Per-Output Voltage Control	Each of four output banks powered separately (1.5/1.8/2.5/3.3 V), eliminating level-shifter ICs in multi-voltage FPGA/ASIC systems
Glitchless Frequency Tuning	Independent 1 ppm-step frequency increment/decrement via pin or I²C, with sub-ns update latency
Programmable Phase Offset	±45 ns adjustment per output with <20 ps resolution, enabling precise skew management in SerDes lanes
Spread Spectrum Clocking	Configurable on any output: 0.5–5.0% down-spread, 33–63 kHz modulation rate-reduces EMI without affecting timing margins

Applications

PCIe Gen 4 Switch Timing	Ethernet Switch/Routing
Use Scenario: High-density 32-lane PCIe Gen 4 switch ASIC requiring synchronized, low-jitter clocks for multiple SerDes lanes and memory interfaces. IC Role / Device Role / Timing Role: Primary clock generator providing four independent 100 MHz HCSL clocks with <0.45 ps RMS jitter and matched phase alignment. Use Value: Enables full Gen 4 compliance without external jitter cleaners; eliminates need for four discrete oscillators and reduces BOM count by 75%.	Use Scenario: 10 GbE/25 GbE line card with multi-port MAC/PHY and packet buffer controllers needing scalable, reconfigurable clock trees. IC Role / Device Role / Timing Role: Configurable clock source delivering 156.25 MHz (10GBase-R), 312.5 MHz (25GBase-R), and 125 MHz (GbE) simultaneously with independent voltage domains. Use Value: Single-device support for mixed-speed Ethernet standards; dynamic reconfiguration via I²C enables field-upgradable timing profiles.
Broadcast Video Timing	FPGA-Based Processor Clocking
Use Scenario: SMPTE ST 2082/ST 2081 video transport system requiring ultra-low-jitter, phase-aligned 27 MHz, 74.25 MHz, and 148.5 MHz clocks for encoder/decoder chains. IC Role / Device Role / Timing Role: Precision timing hub generating three broadcast-grade frequencies with <10 ps pk-pk period jitter and <20 ps inter-output skew. Use Value: Meets SMPTE RP 184 jitter limits; eliminates external phase-locked loops and simplifies board layout with integrated synthesis.	Use Scenario: Xilinx Versal or Intel Agilex FPGA platform requiring multiple clock domains (logic, transceivers, DDR, PCIe) with independent voltage and format control. IC Role / Device Role / Timing Role: Centralized clock manager supplying LVDS (100 MHz), HCSL (300 MHz), and CMOS (50 MHz) clocks at 1.8 V, 2.5 V, and 3.3 V respectively. Use Value: Eliminates discrete clock buffers and level shifters; ClockBuilder Pro GUI accelerates FPGA timing closure during development.

PCIe Gen 4 Switch Timing

Ethernet Switch/Routing

Use Scenario: High-density 32-lane PCIe Gen 4 switch ASIC requiring synchronized, low-jitter clocks for multiple SerDes lanes and memory interfaces.

IC Role / Device Role / Timing Role: Primary clock generator providing four independent 100 MHz HCSL clocks with <0.45 ps RMS jitter and matched phase alignment.

Use Value: Enables full Gen 4 compliance without external jitter cleaners; eliminates need for four discrete oscillators and reduces BOM count by 75%.

Use Scenario: 10 GbE/25 GbE line card with multi-port MAC/PHY and packet buffer controllers needing scalable, reconfigurable clock trees.

IC Role / Device Role / Timing Role: Configurable clock source delivering 156.25 MHz (10GBase-R), 312.5 MHz (25GBase-R), and 125 MHz (GbE) simultaneously with independent voltage domains.

Use Value: Single-device support for mixed-speed Ethernet standards; dynamic reconfiguration via I²C enables field-upgradable timing profiles.

Broadcast Video Timing

FPGA-Based Processor Clocking

Use Scenario: SMPTE ST 2082/ST 2081 video transport system requiring ultra-low-jitter, phase-aligned 27 MHz, 74.25 MHz, and 148.5 MHz clocks for encoder/decoder chains.

IC Role / Device Role / Timing Role: Precision timing hub generating three broadcast-grade frequencies with <10 ps pk-pk period jitter and <20 ps inter-output skew.

Use Value: Meets SMPTE RP 184 jitter limits; eliminates external phase-locked loops and simplifies board layout with integrated synthesis.

Use Scenario: Xilinx Versal or Intel Agilex FPGA platform requiring multiple clock domains (logic, transceivers, DDR, PCIe) with independent voltage and format control.

IC Role / Device Role / Timing Role: Centralized clock manager supplying LVDS (100 MHz), HCSL (300 MHz), and CMOS (50 MHz) clocks at 1.8 V, 2.5 V, and 3.3 V respectively.

Use Value: Eliminates discrete clock buffers and level shifters; ClockBuilder Pro GUI accelerates FPGA timing closure during development.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output programmable clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D06989-GM	Higher integration: includes integrated LDOs, enhanced PCIe Gen 5 jitter performance (0.1 ps RMS), and 6-output capability	Targeted at next-gen AI accelerators and CXL-based systems requiring tighter jitter and more outputs	Select when Gen 5 compliance, lower jitter, or >4 outputs are required; higher cost and larger 32-QFN footprint
ICS8430I-01LG	Fixed-frequency, non-programmable quad LVDS clock fanout buffer; no synthesis or voltage flexibility	Limited to static clock distribution; no frequency translation or spread spectrum	Choose only for simple, low-cost clock replication where reprogrammability and multi-format support are unnecessary

Compared with Si5332A-D06989-GM, SI5338P-B04725-GM offers broader input flexibility and lower cost for Gen 4 systems, while ICS8430I-01LG lacks synthesis entirely-making SI5338P-B04725-GM the optimal balance of programmability, jitter performance, and cost for industrial PCIe and Ethernet timing.

Availability

SI5338P-B04725-GM is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, 10/25 GbE routing, and broadcast video synchronization requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for SI5338P-B04725-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, mobile, infrastructure, and timing solutions with over 40 years of RF and clock innovation.

The Si5338 family was designed specifically for high-performance, multi-protocol serial interface timing-including PCIe, Ethernet, Fibre Channel, and broadcast video-where low jitter, programmability, and output flexibility are critical.

FAQ

What is the maximum output frequency supported by the SI5338P-B04725-GM?

The SI5338P-B04725-GM supports up to 710 MHz on LVPECL/LVDS/CML outputs, 350 MHz on SSTL/HSTL, 250 MHz on HCSL, and 200 MHz on CMOS. Frequencies above 350 MHz are limited to two unique values simultaneously (Fvco/4 and Fvco/6), as specified in the Skyworks Rev. 1.6 datasheet Section 3.3.

Does the SI5338P-B04725-GM support PCIe Gen 4 Common Clock compliance?

Yes, the SI5338P-B04725-GM delivers 0.15–0.45 ps RMS jitter (10 kHz–50 MHz) in HCSL 100 MHz output mode, fully meeting PCIe Base Specification 4.0 common clock requirements. This is verified using the Skyworks PCIe Clock Jitter Tool and Intel Clock Jitter Tool v1.6.4 per AN562.

Can the SI5338P-B04725-GM generate different output voltages simultaneously?

Yes-the SI5338P-B04725-GM provides four independent VDDO supplies (VDDO0–VDDO3), each configurable for 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This allows simultaneous LVDS (2.5 V), HCSL (1.8 V), and CMOS (3.3 V) outputs without external level shifters.

How is the SI5338P-B04725-GM programmed, and is external non-volatile memory required?

The SI5338P-B04725-GM is programmed via I²C/SMBus interface using Skyworks' ClockBuilder Pro software. Configuration is stored in on-chip OTP NVM, so no external EEPROM or flash is needed-power-on initialization is autonomous after programming.

What input reference options does the SI5338P-B04725-GM support?

The SI5338P-B04725-GM accepts eight input types: 8–30 MHz crystal, 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL, and 5–710 MHz differential (LVDS/LVPECL/CML). Dual differential inputs (IN1/IN2 and IN5/IN6) enable failover or frequency translation architectures.

SI5338P-B04725-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tray

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338P-B04725-GM FAQ

1.How can I place an order for SI5338P-B04725-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338P-B04725-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338P-B04725-GM reliable?

The price and inventory of SI5338P-B04725-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338P-B04725-GM is usually 5 days.

3.What payment methods are accepted for SI5338P-B04725-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338P-B04725-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338P-B04725-GM?

SI5338P-B04725-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338P-B04725-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338P-B04725-GM?

For technical support, including SI5338P-B04725-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338P-B04725-GM requirements.

6.How does Aetrix verify that SI5338P-B04725-GM is sourced from the original manufacturer or authorized distributors?

All SI5338P-B04725-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338P-B04725-GM meets industry standards.

7.What is the process for return or replacement of SI5338P-B04725-GM?

All SI5338P-B04725-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338P-B04725-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338P-B04725-GM part is unused and in its original packaging.

Return procedure for SI5338P-B04725-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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