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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338P-B04734-GMR

Name: SI5338P-B04734-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338P-B04734-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338P-B04734-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338P-B04734-GMR.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5338P-B04734-GMR from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation across –40 to +85 °C. It replaces up to four crystal oscillators in high-speed serial interface timing applications such as PCIe root complexes and FPGA-based compute platforms.

For engineers reviewing the SI5338P-B04734-GMR datasheet, SI5338P-B04734-GMR pinout, SI5338P-B04734-GMR application, or SI5338P-B04734-GMR equivalent, key selection criteria include its MultiSynth™-based any-frequency synthesis (0.16–710 MHz per output), independent output voltage support (1.5/1.8/2.5/3.3 V), spread-spectrum capability (0.5–5.0% down-spread), and 24-QFN package compatibility with space-constrained PCB layouts.

Technical Context

The SI5338P-B04734-GMR implements a two-stage PLL architecture: a high-stability reference stage followed by four independent MultiSynth™ fractional-N synthesis blocks, each driving one output pair (CLKxA/CLKxB). Its input flexibility supports crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), and differential (5–710 MHz) references.

Each output driver supports LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats with programmable slew rate, drive strength, and termination, plus independent phase adjustment (<20 ps steps) and frequency increment/decrement (1 ppm steps). The device operates from a single 1.8/2.5/3.3 V core supply with 45 mA typical current draw and includes loss-of-lock and loss-of-signal alarms.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps - meets PCIe Gen 3 SRNS and Gen 4 common clock jitter requirements for high-reliability serial link timing
Output Frequency Range	0.16–710 MHz - covers Ethernet (125/156.25 MHz), PCIe (100 MHz), Fibre Channel (1.0625 GHz ÷ 2 = 531.25 MHz), and processor clocks
Input Reference Support	Crystal (8–30 MHz), CMOS (5–200 MHz), differential (5–710 MHz) - enables flexible system-level clock tree design without external buffers
Output Formats	LVPECL, LVDS, HCSL, CMOS, SSTL, HSTL - allows direct interface to FPGAs, ASICs, SerDes PHYs, and memory controllers
Supply Voltage	Core: 1.8/2.5/3.3 V; Output buffers: 1.4–3.63 V - supports mixed-voltage SoC/FPGA platforms with independent I/O domain control
Package	24-pin QFN, 4 × 4 mm - surface-mount compatible with automated assembly and thermal performance of θJA = 37 °C/W
Operating Temperature	–40 to +85 °C - qualified for industrial and telecom line card environments without derating

Pinout & Package

SI5338P-B04734-GMR is housed in a 24-lead, 4 × 4 mm QFN package with exposed thermal pad. Pin assignments follow Skyworks' standard Si5338 pinout: dual differential inputs (IN1/IN2, IN5/IN6), two single-ended inputs (IN3, IN4), four differential output pairs (CLK0A/CLK0B through CLK3A/CLK3B), three independent VDDO supplies (VDDO0–VDDO3), shared VDD core, I²C interface (SCL/SDA), interrupt (INTR), and reserved ground (RSVD_GND).

Pin/Terminal	Circuit Role	Design Meaning
IN1 / IN2	Differential reference input pair	Accepts 5–710 MHz AC-coupled differential clock; internal 100 Ω termination enables direct connection to oscillator or SerDes output
CLK0A / CLK0B	Differential output pair 0	Configurable as LVPECL/LVDS/HCSL; independently set frequency, format, voltage, and phase offset
VDDO0	Output buffer supply for CLK0A/B	Decouples noise from core supply; supports 1.5–3.3 V to match connected IC's I/O voltage
SCL / SDA	I²C/SMBus programming interface	Allows in-system configuration at power-up or runtime; supports ClockBuilder Pro GUI and register-level firmware updates
INTR	Interrupt output	Asserts low on loss-of-lock or loss-of-signal events; enables real-time system fault monitoring without polling

Key Features

Feature	Design Value
MultiSynth™ synthesis	Four independent fractional-N synthesizers enable true zero-ppm accuracy on all outputs without external VCXOs or trimming
PCIe Gen 4 compliance	0.15–0.45 ps RMS jitter in common clock mode satisfies PCI-SIG® Gen 4 specification for root complex and endpoint timing
Independent output voltage control	Each VDDOx pin powers one output pair, allowing simultaneous 1.8 V FPGA clocking and 3.3 V legacy peripheral timing
Glitchless frequency tuning	Pin-controlled 1 ppm step increments/decrements enable dynamic clock scaling during thermal or load transients without output interruption
Programmable spread spectrum	Configurable 0.5–5.0% down-spread at 33–63 kHz reduces EMI peak emissions in dense PCB layouts without affecting timing margin
External feedback mode	Supports zero-delay buffer operation by routing CLKOUT back to FB input, eliminating propagation delay in synchronous fanout trees

Applications

PCIe Gen 3/4 Root Complex	Ethernet Switch Timing
Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe endpoints and switch fabric in a 1U server motherboard. IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent, low-jitter PCIe-compliant clocks with matched skew and spread-spectrum EMI reduction. Use Value: Eliminates four discrete oscillators while meeting PCIe Gen 4 SRNS jitter spec (≤0.32 ps RMS) and enabling board-level EMI certification.	Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10/25 GbE switch ASICs and PHYs in a carrier-grade aggregation switch. IC Role / Device Role / Timing Role: Any-frequency synthesizer producing exact IEEE 802.3-compliant rates from a single 25 MHz crystal reference. Use Value: Reduces BOM count and layout area versus multiple fixed-frequency XO solutions; supports multi-rate port provisioning via software reconfiguration.
FPGA-Based Video Processing	Telecom Line Card Synchronization
Use Scenario: Supplying pixel clock (148.5 MHz), DDR3 memory clock (400 MHz), and HDMI TMDS clock (297 MHz) to a broadcast video encoder FPGA. IC Role / Device Role / Timing Role: Programmable quad clock source with independent voltage and format per output to match heterogeneous FPGA I/O banks. Use Value: Enables single-device timing for mixed-voltage (1.8 V I/O, 1.5 V memory, 3.3 V interface) FPGA designs without level-shifting or external buffers.	Use Scenario: Delivering stratum-3 compliant 2.048 MHz, 19.44 MHz, and 155.52 MHz clocks to TDM framer, packet processor, and SerDes in a 40G OTN line card. IC Role / Device Role / Timing Role: High-stability clock generator supporting both synchronous (SONET/SDH) and packet-based (SyncE) timing architectures. Use Value: Meets OC-12 random jitter spec (≤1 ps RMS) and supports holdover via internal NVM configuration, reducing dependency on external timing modules.

PCIe Gen 3/4 Root Complex

Ethernet Switch Timing

Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe endpoints and switch fabric in a 1U server motherboard.

IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent, low-jitter PCIe-compliant clocks with matched skew and spread-spectrum EMI reduction.

Use Value: Eliminates four discrete oscillators while meeting PCIe Gen 4 SRNS jitter spec (≤0.32 ps RMS) and enabling board-level EMI certification.

Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10/25 GbE switch ASICs and PHYs in a carrier-grade aggregation switch.

IC Role / Device Role / Timing Role: Any-frequency synthesizer producing exact IEEE 802.3-compliant rates from a single 25 MHz crystal reference.

Use Value: Reduces BOM count and layout area versus multiple fixed-frequency XO solutions; supports multi-rate port provisioning via software reconfiguration.

FPGA-Based Video Processing

Telecom Line Card Synchronization

Use Scenario: Supplying pixel clock (148.5 MHz), DDR3 memory clock (400 MHz), and HDMI TMDS clock (297 MHz) to a broadcast video encoder FPGA.

IC Role / Device Role / Timing Role: Programmable quad clock source with independent voltage and format per output to match heterogeneous FPGA I/O banks.

Use Value: Enables single-device timing for mixed-voltage (1.8 V I/O, 1.5 V memory, 3.3 V interface) FPGA designs without level-shifting or external buffers.

Use Scenario: Delivering stratum-3 compliant 2.048 MHz, 19.44 MHz, and 155.52 MHz clocks to TDM framer, packet processor, and SerDes in a 40G OTN line card.

IC Role / Device Role / Timing Role: High-stability clock generator supporting both synchronous (SONET/SDH) and packet-based (SyncE) timing architectures.

Use Value: Meets OC-12 random jitter spec (≤1 ps RMS) and supports holdover via internal NVM configuration, reducing dependency on external timing modules.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D06734-GM	Higher integration: 8 outputs, integrated jitter cleaner, lower 0.35 ps RMS jitter; requires external 100 MHz reference for optimal performance	Better suited for ultra-low-jitter 100G/400G optical modules where sub-0.4 ps RMS is mandatory	Select when PCIe Gen 5 or IEEE 1588 boundary clock requirements demand <0.4 ps RMS jitter and >8 outputs are needed
ICS853S02IAGLF	Fixed-frequency, non-programmable; 2 LVDS outputs only; 1.2 ps RMS jitter; no I²C interface or spread spectrum	Limited to static clock fanout in cost-sensitive industrial controllers where frequency agility is unnecessary	Choose only for simple 1:2 LVDS fanout with no configuration needs-lacks any-frequency synthesis or multi-format support

Compared with SI5338P-B04734-GMR, the Si5332A offers superior jitter and scalability but increases system complexity and cost, while the ICS853S02 provides minimal functionality at lower price-neither matches the balance of programmability, jitter performance, and output flexibility delivered by the SI5338P-B04734-GMR.

Availability

SI5338P-B04734-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 server platforms, 25G/100G Ethernet switches, and FPGA-based broadcast video equipment requiring stable component supply, long-term lifecycle assurance, and full traceability.

Supply support for SI5338P-B04734-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and mobile markets.

The Si5338 family was designed as a programmable, low-jitter clock generator platform for high-speed serial interfaces-including PCIe, Ethernet, Fibre Channel, and broadcast video-where flexibility, precision, and integration reduce system-level timing complexity.

FAQ

What is the maximum output frequency supported by SI5338P-B04734-GMR?

The SI5338P-B04734-GMR supports up to 710 MHz on LVPECL/LVDS/CML outputs, 350 MHz on SSTL/HSTL, 250 MHz on HCSL, and 200 MHz on CMOS. Frequencies above 350 MHz are limited to two unique values simultaneously (Fvco/4 and Fvco/6) due to VCO architecture constraints. All outputs maintain ≤1 ps RMS jitter within their respective rated ranges.

Does SI5338P-B04734-GMR support PCIe Gen 4 Common Clock mode?

Yes, SI5338P-B04734-GMR is explicitly validated for PCIe Gen 4 Common Clock mode with 0.15–0.45 ps RMS jitter (10 kHz–50 MHz bandwidth), meeting the PCI-SIG® Base Specification 4.0 rev. 0.5 requirement. This validation applies to HCSL 100 MHz outputs with PLL loop bandwidth set to 2–4 MHz and CDR at 10 MHz.

Can SI5338P-B04734-GMR generate different output voltages on separate pins?

Yes, SI5338P-B04734-GMR provides independent VDDO0–VDDO3 pins, each powering one output pair (CLK0A/B through CLK3A/B). Each VDDO pin accepts 1.4–3.63 V, enabling simultaneous 1.8 V LVDS for an FPGA and 3.3 V CMOS for a microcontroller without external level shifters.

How is SI5338P-B04734-GMR programmed in-system?

SI5338P-B04734-GMR uses an I²C/SMBus-compatible 2-wire interface (SCL/SDA) for in-system programming. Configuration is typically performed using Skyworks' ClockBuilder Pro software, which generates register maps and .c files for embedded initialization. The device retains settings in one-time-programmable (OTP) NVM for automatic boot-up.

What is the thermal performance of SI5338P-B04734-GMR in its 4 × 4 mm QFN package?

SI5338P-B04734-GMR has a junction-to-ambient thermal resistance (θJA) of 37 °C/W under still-air conditions and junction-to-case (θJC) of 10 °C/W. With typical 45 mA core current and 3.3 V supply, power dissipation remains below 150 mW, enabling reliable operation up to +85 °C ambient without forced airflow or heatsinking.

SI5338P-B04734-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338P-B04734-GMR FAQ

1.How can I place an order for SI5338P-B04734-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338P-B04734-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338P-B04734-GMR reliable?

The price and inventory of SI5338P-B04734-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338P-B04734-GMR is usually 5 days.

3.What payment methods are accepted for SI5338P-B04734-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338P-B04734-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338P-B04734-GMR?

SI5338P-B04734-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338P-B04734-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338P-B04734-GMR?

For technical support, including SI5338P-B04734-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338P-B04734-GMR requirements.

6.How does Aetrix verify that SI5338P-B04734-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338P-B04734-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338P-B04734-GMR meets industry standards.

7.What is the process for return or replacement of SI5338P-B04734-GMR?

All SI5338P-B04734-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338P-B04734-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338P-B04734-GMR part is unused and in its original packaging.

Return procedure for SI5338P-B04734-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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