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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338P-B05982-GM

Name: SI5338P-B05982-GM
Brand: Skyworks Solutions Inc.
SKU: SI5338P-B05982-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338P-B05982-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338P-B05982-GM.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

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Product details

Overview

SI5338P-B05982-GM from Skyworks Solutions is a quad-output, I²C-programmable clock generator using MultiSynth™ technology to synthesize any frequency on each of four independent differential outputs (CLK0A/B through CLK3A/B), supporting LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats at 0.16–710 MHz, with 0.7 ps RMS typical phase jitter and PCIe Gen 1–4 Common Clock & Gen 3 SRNS compliance. It replaces up to four crystal oscillators in high-speed serial interface timing applications.

For engineers reviewing the SI5338P-B05982-GM datasheet, SI5338P-B05982-GM pinout, SI5338P-B05982-GM application, or SI5338P-B05982-GM equivalent, key selection criteria include its 4× independent output configurability per voltage (1.5/1.8/2.5/3.3 V), ±20 ps phase step resolution, 1 ppm frequency increment/decrement capability, spread-spectrum support (0.5–5.0% at 33–63 kHz), and 24-QFN package compatibility with PCIe, Ethernet, and FPGA clocking systems.

Technical Context

The SI5338P-B05982-GM implements a two-stage synthesis architecture: a PLL-based Stage 1 (with 1.6 MHz loop bandwidth) locks to one of six input references (crystal, CMOS, SSTL/HSTL, or differential), followed by four independent MultiSynth™ fractional-N dividers (Stage 2) for precise output frequency generation. Each output driver supports format- and voltage-selectable termination with programmable slew rate control.

It integrates non-volatile memory (OTP) for factory or field programming via I²C/SMBus, supports loss-of-lock and loss-of-signal alarms, and enables glitchless real-time frequency/phase adjustments via dedicated pins (FINC/FDEC, PINC/PDEC) or register writes - critical for dynamic clock management in telecom line cards and MSAN systems.

Key Specifications

Parameter	Value and Actual Design Meaning
Output Count	Four independent differential clock outputs (CLK0A/B–CLK3A/B), configurable as eight single-ended or mixed-mode signals
Frequency Range	0.16–710 MHz per output; supports >350 MHz only on Fvco/4 and Fvco/6 simultaneously
Phase Jitter (RMS)	0.7 ps typical (12 kHz–20 MHz), meeting PCIe Gen 3 SRNS and GbE jitter requirements
Input Flexibility	Supports 8–30 MHz crystal, 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL, or 5–710 MHz differential reference
Supply Voltages	Core: 1.8/2.5/3.3 V; Output buffers: independently selectable 1.5/1.8/2.5/3.3 V per driver
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch, exposed thermal pad
Operating Temp	–40 °C to +85 °C ambient, suitable for industrial and telecom infrastructure environments

Pinout & Package

SI5338P-B05982-GM uses a 24-lead QFN package (4 mm × 4 mm, 0.5 mm pitch) with an exposed thermal pad. Pin assignments are fixed across Si5338 variants and validated per Skyworks Rev. 1.6 datasheet Figure 1 (Top View).

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2, IN5, IN6	Differential input pairs	Accept 5–710 MHz AC-coupled differential clocks; require external 100 Ω termination
IN3, IN4	Single-ended input pins	Support 5–200 MHz CMOS inputs; VIH = 0.7×VDD, VIL = 0.3×VDD
CLK0A–CLK3B (x4 pairs)	Differential clock outputs	Each pair supports LVPECL/LVDS/HCSL/CML/SSTL/HSTL; voltage per driver set via VDDOx
VDDO0–VDDO3	Output buffer supplies	Independent 1.5/1.8/2.5/3.3 V rails per output bank - enables mixed-voltage system interfacing
VDD	Core supply	Single 1.8/2.5/3.3 V rail powers PLL, logic, and NVM; PSRR optimized for noise immunity
SCL, SDA	I²C interface	Standard SMBus-compatible 100/400 kHz operation; supports ClockBuilder Pro configuration
INTR	Interrupt output	Open-drain status indicator for loss-of-lock or loss-of-signal events

Key Features

Feature	Design Value
MultiSynth™ synthesis	Enables true zero-ppm frequency accuracy on all four outputs without external crystals or VCXOs
Independent output voltage per driver	Eliminates level-shifting components when driving mixed-voltage FPGAs, ASICs, or SerDes blocks
Programmable phase offset (±45 ns)	Allows deterministic skew compensation across multi-lane interfaces like PCIe or Ethernet PHYs
Glitchless frequency adjustment	1 ppm steps via FINC/FDEC pins enable real-time clock tuning without output interruption
Spread spectrum (SSC)	Configurable 0.5–5.0% down-spread at 33–63 kHz reduces EMI in dense PCB layouts
External feedback mode	Supports zero-delay operation for clock distribution networks requiring minimal propagation latency

Applications

PCIe Gen 3/4 Timing	Ethernet Switch Clocking
Use Scenario: Providing synchronized 100 MHz common clock and 125 MHz reference for multiple PCIe Gen 4 endpoints and root complexes in server backplanes. IC Role / Device Role / Timing Role: Quad-output clock generator delivering compliant PCIe Common Clock and SRNS signals with <0.32 ps RMS jitter. Use Value: Eliminates need for four discrete oscillators while maintaining Gen 4 jitter margin and enabling per-slot frequency margining.	Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1G/10G/25G Ethernet PHYs and switch fabric ASICs in modular routers. IC Role / Device Role / Timing Role: Programmable frequency translator converting a single 25 MHz crystal into multiple Ethernet-compliant rates. Use Value: Reduces BOM count and layout area versus discrete clock trees; supports IEEE 802.3bj jitter requirements via low-phase-noise synthesis.
FPGA/ASIC Clock Distribution	Broadcast Video Timing
Use Scenario: Supplying 100 MHz system clock, 200 MHz DDR interface clock, 300 MHz transceiver reference, and 400 MHz video processing clock to Xilinx Versal or Intel Agilex devices. IC Role / Device Role / Timing Role: Configurable quad clock source with independent voltage and format per output to match diverse FPGA I/O banks. Use Value: Avoids external level shifters and simplifies power sequencing; enables dynamic reconfiguration via I²C during FPGA bitstream loading.	Use Scenario: Delivering SMPTE ST 2082 (12G-SDI) 742.5 MHz, ST 2081 (6G-SDI) 371.25 MHz, and ST 292 (HD-SDI) 148.5 MHz clocks to broadcast camera processors and frame synchronizers. IC Role / Device Role / Timing Role: High-frequency, low-jitter clock generator supporting exact SDI line rates with sub-10 ps cycle-cycle jitter. Use Value: Meets SMPTE jitter masks without external jitter cleaners; enables single-chip timing for multi-standard video equipment.

PCIe Gen 3/4 Timing

Ethernet Switch Clocking

Use Scenario: Providing synchronized 100 MHz common clock and 125 MHz reference for multiple PCIe Gen 4 endpoints and root complexes in server backplanes.

IC Role / Device Role / Timing Role: Quad-output clock generator delivering compliant PCIe Common Clock and SRNS signals with <0.32 ps RMS jitter.

Use Value: Eliminates need for four discrete oscillators while maintaining Gen 4 jitter margin and enabling per-slot frequency margining.

Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1G/10G/25G Ethernet PHYs and switch fabric ASICs in modular routers.

IC Role / Device Role / Timing Role: Programmable frequency translator converting a single 25 MHz crystal into multiple Ethernet-compliant rates.

Use Value: Reduces BOM count and layout area versus discrete clock trees; supports IEEE 802.3bj jitter requirements via low-phase-noise synthesis.

FPGA/ASIC Clock Distribution

Broadcast Video Timing

Use Scenario: Supplying 100 MHz system clock, 200 MHz DDR interface clock, 300 MHz transceiver reference, and 400 MHz video processing clock to Xilinx Versal or Intel Agilex devices.

IC Role / Device Role / Timing Role: Configurable quad clock source with independent voltage and format per output to match diverse FPGA I/O banks.

Use Value: Avoids external level shifters and simplifies power sequencing; enables dynamic reconfiguration via I²C during FPGA bitstream loading.

Use Scenario: Delivering SMPTE ST 2082 (12G-SDI) 742.5 MHz, ST 2081 (6G-SDI) 371.25 MHz, and ST 292 (HD-SDI) 148.5 MHz clocks to broadcast camera processors and frame synchronizers.

IC Role / Device Role / Timing Role: High-frequency, low-jitter clock generator supporting exact SDI line rates with sub-10 ps cycle-cycle jitter.

Use Value: Meets SMPTE jitter masks without external jitter cleaners; enables single-chip timing for multi-standard video equipment.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output programmable clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D06982-GM	Higher integration: includes integrated crystal, lower jitter (0.35 ps RMS), supports up to 10 outputs with dual-loop architecture	Better suited for ultra-low-jitter applications (e.g., 400G optical modules); requires no external crystal	Select if crystal integration and sub-0.4 ps jitter are required; higher cost and larger footprint (32-QFN)
ICS8430I-01T	Fixed-frequency, non-programmable quad LVDS clock buffer; no synthesis capability; 1.2 ps RMS jitter	Limited to static clock fanout; no frequency translation or I²C configuration	Choose only for simple clock distribution where frequencies are fixed and programmability is unnecessary

Compared with Si5332A-D06982-GM, SI5338P-B05982-GM offers greater design flexibility with external crystal choice and broader input range but trades off ~0.35 ps RMS jitter and crystal integration. Against ICS8430I-01T, it provides full frequency synthesis and dynamic control at the cost of higher complexity and power - making SI5338P-B05982-GM optimal for systems requiring multi-rate, multi-format, and field-reprogrammable timing.

Availability

SI5338P-B05982-GM is available at Aetrix Electronics and suitable for PCIe Gen 4 server motherboards, 10G/25G Ethernet switches, and FPGA-based broadcast video equipment requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for SI5338P-B05982-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, mobile, infrastructure, and timing solutions with over 30 years of RF and clocking expertise.

The Si5338 product line was designed specifically for high-performance, multi-protocol serial interface timing - targeting PCIe, Ethernet, Fibre Channel, and broadcast video systems needing flexible, low-jitter, software-configurable clock generation in compact form factors.

FAQ

What is the primary function of the SI5338P-B05982-GM in a timing architecture?

The SI5338P-B05982-GM serves as a quad-output, I²C-programmable clock generator that synthesizes any frequency on each of its four independent differential outputs using Skyworks' MultiSynth™ technology. It replaces multiple discrete oscillators or clock buffers, providing precise, low-jitter clocks for PCIe, Ethernet, FPGA, and broadcast video systems. Its core value lies in eliminating crystal dependencies while maintaining 0 ppm frequency accuracy and sub-1 ps RMS jitter - directly implemented in the SI5338P-B05982-GM's architecture.

Does the SI5338P-B05982-GM support PCIe Gen 4 Common Clock compliance?

Yes, the SI5338P-B05982-GM meets PCIe Gen 4 Common Clock specifications with ≤0.45 ps RMS jitter (10 kHz–50 MHz) when configured per Skyworks AN562 guidelines using HCSL outputs and appropriate PLL bandwidth (2–4 MHz). This compliance is verified per PCI-SIG Base Specification 4.0 rev. 0.5 and confirmed in Table 12 of the official SI5338 datasheet - a guaranteed performance attribute of the SI5338P-B05982-GM variant.

Can the SI5338P-B05982-GM generate different output voltages simultaneously?

Yes, the SI5338P-B05982-GM supports independent output supply voltages per driver bank: VDDO0 for CLK0A/B, VDDO1 for CLK1A/B, VDDO2 for CLK2A/B, and VDDO3 for CLK3A/B. Each can be set to 1.5 V, 1.8 V, 2.5 V, or 3.3 V, enabling direct interfacing with mixed-voltage FPGAs, ASICs, or SerDes blocks without external level shifters - a confirmed capability documented in the "Output Stage" section (page 21) and Table 6 of the SI5338P-B05982-GM datasheet.

How is the SI5338P-B05982-GM programmed and configured?

The SI5338P-B05982-GM is programmed via its I²C/SMBus-compatible interface (SCL/SDA pins) using Skyworks' ClockBuilder Pro software, which generates configuration files and registers settings for OTP or RAM loading. Factory programming is supported, and field updates are possible without hardware changes. All configuration parameters - including frequency, format, voltage, phase, and spread spectrum - are stored in on-chip non-volatile memory, ensuring repeatable startup behavior for the SI5338P-B05982-GM.

What is the maximum output frequency supported by the SI5338P-B05982-GM in LVPECL mode?

The SI5338P-B05982-GM supports LVPECL outputs up to 710 MHz, as specified in Table 6 of the datasheet under "Output Clocks (Differential)" for LVPECL/LVDS/CML formats. However, only two unique frequencies above 350 MHz (e.g., Fvco/4 and Fvco/6) may be generated simultaneously due to VCO constraints - a hard architectural limit confirmed for the SI5338P-B05982-GM and not dependent on external circuitry.

SI5338P-B05982-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tray

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338P-B05982-GM FAQ

1.How can I place an order for SI5338P-B05982-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338P-B05982-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338P-B05982-GM reliable?

The price and inventory of SI5338P-B05982-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338P-B05982-GM is usually 5 days.

3.What payment methods are accepted for SI5338P-B05982-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338P-B05982-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338P-B05982-GM?

SI5338P-B05982-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338P-B05982-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338P-B05982-GM?

For technical support, including SI5338P-B05982-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338P-B05982-GM requirements.

6.How does Aetrix verify that SI5338P-B05982-GM is sourced from the original manufacturer or authorized distributors?

All SI5338P-B05982-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338P-B05982-GM meets industry standards.

7.What is the process for return or replacement of SI5338P-B05982-GM?

All SI5338P-B05982-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338P-B05982-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338P-B05982-GM part is unused and in its original packaging.

Return procedure for SI5338P-B05982-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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