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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338P-B05982-GMR

Name: SI5338P-B05982-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338P-B05982-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338P-B05982-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338P-B05982-GMR.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5338P-B05982-GMR from Skyworks Solutions is a quad-output, I²C-programmable clock generator with MultiSynth™ frequency synthesis, delivering four independent differential or single-ended clocks (0.16–710 MHz), 0.7 ps RMS phase jitter (typ), PCIe Gen 1–4 and SRNS compliance, and operation from 1.8/2.5/3.3 V core supply in a 4×4 mm 24-QFN package. It replaces multiple crystal oscillators in high-speed serial interface timing applications.

For engineers reviewing the SI5338P-B05982-GMR datasheet, SI5338P-B05982-GMR pinout, SI5338P-B05982-GMR application, or SI5338P-B05982-GMR equivalent, key selection criteria include its 4-output any-frequency synthesis capability, PCIe Gen 4 common-clock jitter performance (0.15–0.45 ps RMS), independent output voltage per driver (1.5–3.3 V), spread-spectrum control (0.5–5.0% down-spread), and I²C/SMBus programmability with ClockBuilder Pro support.

Technical Context

The SI5338P-B05982-GMR implements a two-stage PLL architecture: a high-stability reference stage followed by four independent MultiSynth™ fractional-N synthesizers, each driving a configurable output buffer. Its synthesis resolution is 1 ppb, supporting true zero-ppm accuracy across all outputs.

It supports flexible input references - external crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), or differential (5–710 MHz) - and enables glitchless frequency adjustment in 1 ppm steps and phase tuning in <20 ps increments per output. Loss-of-lock and loss-of-signal alarms provide real-time status monitoring.

Key Specifications

Parameter	Value and Actual Design Meaning
Output count & type	4 independent outputs; configurable as LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL
Frequency range	0.16–710 MHz per output; up to two >350 MHz frequencies simultaneously (Fvco/4 & Fvco/6)
Phase jitter (RMS)	0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 4 common-clock spec (0.15–0.45 ps RMS)
Supply voltages	Core: 1.8/2.5/3.3 V ±10%; Output buffers: independently selectable 1.5/1.8/2.5/3.3 V
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch, exposed thermal pad
Operating temp.	–40 °C to +85 °C ambient; qualified for industrial and telecom line card environments
Interface	I²C/SMBus-compatible serial interface (up to 400 kHz); programmable via ClockBuilder Pro

Pinout & Package

SI5338P-B05982-GMR is housed in a 24-lead, 4×4 mm QFN package with wettable flanks and an exposed thermal pad (GND). Pin 1 is top-left corner (IN1), pin numbering proceeds counterclockwise. The package supports reflow soldering per JEDEC J-STD-020 (peak 260 °C).

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2, IN5, IN6	Differential clock inputs	Accept 5–710 MHz AC-coupled differential signals; require external 100 Ω termination
IN3, IN4	Single-ended clock inputs	Support 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL; VIH = 0.7×VDD, VIL = 0.3×VDD
CLK0A–CLK3B	Differential output pairs	Four independent output drivers; each pair configurable for LVPECL/LVDS/HCSL/CML
VDDO0–VDDO3	Output buffer supplies	Independent 1.4–3.63 V supplies per output bank; enable mixed-voltage system interfacing
VDD	Core supply	1.8/2.5/3.3 V ±10%; PSRR optimized for low-noise clock generation
SCL, SDA	I²C interface	Standard bidirectional bus; supports 400 kHz fast-mode; internal pull-ups disabled by default
INTR	Interrupt output	Open-drain status indicator for loss-of-lock, loss-of-signal, or configuration errors
RSVD_GND	Reserved ground	Internal test pin; must be connected to GND per layout guidelines

Key Features

Feature	Design Value
MultiSynth™ synthesis	Four independent fractional-N synthesizers enabling any-frequency output (0.16–710 MHz) with 1 ppb resolution and zero ppm error
PCIe Gen 4 compliance	Meets PCIe Base Spec 4.0 common-clock jitter requirements (0.15–0.45 ps RMS) without external filtering
Configurable spread spectrum	Per-output SSC with adjustable spread (0.5–5.0%), modulation rate (33–63 kHz), and direction (down-spread default)
Glitchless frequency tuning	Independent FINC/FDEC pins enable real-time, sub-ppm frequency adjustments without output interruption
Programmable phase offset	±45 ns initial phase shift per output with <20 ps step resolution for skew alignment in multi-lane interfaces
Flexible reference inputs	Supports crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), and differential (5–710 MHz) sources

Applications

PCIe Gen 4 Switch Timing	Ethernet Switch Clocking
Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe Gen 4 switch ASICs in a 1U data center switch chassis. IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent, low-jitter PCIe-compliant clocks with matched phase alignment. Use Value: Eliminates need for four discrete oscillators; reduces board area by 65% and ensures <100 ps inter-output skew required for Gen 4 link training.	Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 10GbE PHYs, packet processors, and SerDes in a carrier-grade Ethernet switch. IC Role / Device Role / Timing Role: Any-frequency synthesizer producing exact IEEE 802.3-compliant rates from a single 25 MHz crystal reference. Use Value: Achieves 0.7 ps RMS jitter at 125 MHz - 40% below IEEE 802.3bj spec - enabling robust 10GBASE-KR link margin.
Broadcast Video Sync	FPGA Processor Clocking
Use Scenario: Distributing SMPTE ST 2082 (27 Gbps) and ST 2081 (12 Gbps) reference clocks across video processing FPGAs and serializer ICs in a 4K/8K broadcast router. IC Role / Device Role / Timing Role: High-precision clock generator synthesizing 270 MHz, 540 MHz, and 74.25 MHz from one 10 MHz OCXO input. Use Value: Delivers <10 ps cycle-cycle jitter at 270 MHz - critical for maintaining SDI eye diagram integrity over backplane traces.	Use Scenario: Supplying 300 MHz system clock, 200 MHz DDR4 memory clock, and 100 MHz peripheral clock to Xilinx Versal ACAP in a radar signal processing module. IC Role / Device Role / Timing Role: Configurable quad clock source with independent voltage domains (1.8 V for logic, 1.2 V for DDR4) and programmable phase offsets. Use Value: Enables precise setup/hold timing closure across heterogeneous clock domains while reducing BOM count by three discrete oscillators.

PCIe Gen 4 Switch Timing

Ethernet Switch Clocking

Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe Gen 4 switch ASICs in a 1U data center switch chassis.

IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent, low-jitter PCIe-compliant clocks with matched phase alignment.

Use Value: Eliminates need for four discrete oscillators; reduces board area by 65% and ensures <100 ps inter-output skew required for Gen 4 link training.

Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 10GbE PHYs, packet processors, and SerDes in a carrier-grade Ethernet switch.

IC Role / Device Role / Timing Role: Any-frequency synthesizer producing exact IEEE 802.3-compliant rates from a single 25 MHz crystal reference.

Use Value: Achieves 0.7 ps RMS jitter at 125 MHz - 40% below IEEE 802.3bj spec - enabling robust 10GBASE-KR link margin.

Broadcast Video Sync

FPGA Processor Clocking

Use Scenario: Distributing SMPTE ST 2082 (27 Gbps) and ST 2081 (12 Gbps) reference clocks across video processing FPGAs and serializer ICs in a 4K/8K broadcast router.

IC Role / Device Role / Timing Role: High-precision clock generator synthesizing 270 MHz, 540 MHz, and 74.25 MHz from one 10 MHz OCXO input.

Use Value: Delivers <10 ps cycle-cycle jitter at 270 MHz - critical for maintaining SDI eye diagram integrity over backplane traces.

Use Scenario: Supplying 300 MHz system clock, 200 MHz DDR4 memory clock, and 100 MHz peripheral clock to Xilinx Versal ACAP in a radar signal processing module.

IC Role / Device Role / Timing Role: Configurable quad clock source with independent voltage domains (1.8 V for logic, 1.2 V for DDR4) and programmable phase offsets.

Use Value: Enables precise setup/hold timing closure across heterogeneous clock domains while reducing BOM count by three discrete oscillators.

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5341-B-GM	8-output, higher integration (integrated LDOs, dual PLL), 0.35 ps RMS jitter; larger 7×7 mm 48-QFN package	Targeted at multi-ASIC systems requiring >4 clocks or tighter jitter specs (e.g., 5G baseband units)	Select Si5341-B-GM when >4 outputs or sub-0.5 ps jitter is required; SI5338P-B05982-GMR remains optimal for cost-sensitive 4-output PCIe/Ethernet designs.
ICS8430I-01LG	4-output, fixed-frequency (non-programmable), 1.2 ps RMS jitter; supports only LVDS/LVPECL; no spread spectrum or phase tuning	Used in legacy systems where clock frequencies are static and design changes are prohibited	Choose ICS8430I-01LG only for drop-in replacement in existing fixed-frequency designs; SI5338P-B05982-GMR offers field-upgradable flexibility and superior jitter.

Compared with Si5341-B-GM, SI5338P-B05982-GMR provides identical PCIe Gen 4 compliance in a smaller footprint and lower power (45 mA vs. 85 mA), while ICS8430I-01LG lacks programmability and fails to meet Gen 4 jitter targets - making SI5338P-B05982-GMR the balanced choice for new industrial and networking designs requiring configurability, size efficiency, and specification headroom.

Availability

SI5338P-B05982-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, Ethernet switch clocking, and broadcast video synchronization requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for SI5338P-B05982-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and power management ICs for infrastructure, automotive, and mobile markets.

The Si5338 family was designed specifically for high-speed serial interface timing - targeting PCIe, Ethernet, Fibre Channel, and broadcast video systems requiring ultra-low jitter, multi-output flexibility, and field-programmable frequency agility.

FAQ

What is the maximum output frequency supported by SI5338P-B05982-GMR?

The SI5338P-B05982-GMR supports up to 710 MHz on LVPECL/LVDS/CML outputs, 250 MHz on HCSL, and 200 MHz on CMOS. However, only two unique frequencies above 350 MHz can be generated simultaneously - specifically Fvco/4 and Fvco/6 - due to VCO architecture constraints confirmed in Table 6 of the datasheet.

Does SI5338P-B05982-GMR support PCIe Gen 4 Separate Reference No Spread (SRNS) mode?

Yes, SI5338P-B05982-GMR is explicitly compliant with PCIe Gen 3 SRNS and Gen 4 common-clock specifications. Its measured RMS jitter is 0.11–0.32 ps (Gen 3 SRNS) and 0.15–0.45 ps (Gen 4), verified using the Skyworks PCIe Clock Jitter Tool and Intel Clock Jitter Tool v1.6.4 per AN562.

Can SI5338P-B05982-GMR generate different output voltages on each channel?

Yes, SI5338P-B05982-GMR provides four independent VDDOx supplies (VDDO0–VDDO3), each configurable for 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This allows simultaneous interfacing with mixed-voltage devices - e.g., 1.8 V FPGA I/O, 2.5 V SerDes, and 3.3 V control logic - without external level shifters.

What crystal frequency ranges does SI5338P-B05982-GMR support?

SI5338P-B05982-GMR supports external crystals from 8 MHz to 30 MHz, segmented into four validated bands: 8–11 MHz, 11–19 MHz, 19–26 MHz, and 26–30 MHz. Each band specifies recommended load capacitance (17–19 pF) and max ESR (75–300 Ω), per Tables 8–11 in the datasheet.

How is SI5338P-B05982-GMR programmed in-system?

SI5338P-B05982-GMR is programmed via its I²C/SMBus-compatible interface (SCL/SDA pins) operating up to 400 kHz. Configuration is typically performed using Skyworks' ClockBuilder Pro software, which generates register maps and supports EEPROM programming, runtime updates, and jitter optimization profiles for SI5338P-B05982-GMR.

SI5338P-B05982-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338P-B05982-GMR FAQ

1.How can I place an order for SI5338P-B05982-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338P-B05982-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338P-B05982-GMR reliable?

The price and inventory of SI5338P-B05982-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338P-B05982-GMR is usually 5 days.

3.What payment methods are accepted for SI5338P-B05982-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338P-B05982-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338P-B05982-GMR?

SI5338P-B05982-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338P-B05982-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338P-B05982-GMR?

For technical support, including SI5338P-B05982-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338P-B05982-GMR requirements.

6.How does Aetrix verify that SI5338P-B05982-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338P-B05982-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338P-B05982-GMR meets industry standards.

7.What is the process for return or replacement of SI5338P-B05982-GMR?

All SI5338P-B05982-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338P-B05982-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338P-B05982-GMR part is unused and in its original packaging.

Return procedure for SI5338P-B05982-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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